Registration Charges

Registration is OPEN ! Click Here

Tutorial price has been reduced to half (of the price listed below) from Dec 3rd. At this price printed handouts will not be available, however handouts can be purchased at the remaining cost on site.

Registration Cost

The tutorial fee includes the lunch at the venue.
The registration covers all technical session, evening sessions, including breakfast, lunch and dinner for all three days at Hilton.
You may add the following to your registration charge to cover accommodation (this is for 4 nights, independent of whether you stay for 4 nights of less, and can’t be changed).
✓ 4 Nights Stay at Hilton Garden Inn, Single Occupancy (Check-in on Dec. 11th at 3PM and Check-out on Dec. 15th 11AM): ₹35000
✓ 4 Nights Stay at Hilton Garden Inn, Double Occupancy (Check-in on Dec. 11th at 3PM and Check-out on Dec. 15th 11AM): ₹40000
✓ 4 Nights Stay at Hilton Garden Inn, Twin Sharing (Check-in on Dec. 11th at 3PM and Check-out on Dec. 15th 11AM): ₹20000 Per Occupant
✓ (For Student Authors Only) 4 Nights Stay at Hilton Garden Inn, Triple Sharing (Check-in on Dec. 11th at 3PM and Check-out on Dec. 15th 11AM): ₹12000 Per Occupant.
✓ 4 Nights Stay at Hilton Embassy Park, (Check-in on Dec. 11th at 3PM and Check-out on Dec. 15th 11AM): ₹45000

** Those who can’t be accommodated in Hilton Garden Inn (in case of late booking) will be accommodated in Country Inn & Suites by Radisson, which is at a 1km distance.
** The above offer is valid up-to Nov. 20th or till the room availability (whichever is earlier).
** The above pricing is excluding GST (18%) and bank/payment gateway charges (3%) or any other applicable govt. taxes.

£ 29 452 Tickets Available

1.Entrance
2.Coffee Break
3.Lunch on all days

£ 29 452 Tickets Available

1.Entrance
2.Coffee Break
3.Lunch on all days

£ 29 452 Tickets Available

1.Entrance
2.Coffee Break
3.Lunch on all days

Important Dates

Submission Closes

~~7th~~ 18th September

Acceptance of Oral and Poster Papers

7th 16th October

Full Length Paper Submission and Copyright Transfer Deadline

1st November

Technical Program Announcement

25th October 5th November

Author and Speaker Registration Deadline

31st October 5th November

Early Bird Registration Deadline

31st October 10th November

Conference

11th – 14th December

Registration Form

Submit Online

Abstract

Full Paper

Prof. Prashant Murlidhar Sonar

Queensland University of Technology

Bio: Prof. Prashant Sonar is an ARC Future Fellow and Professor in the School of Chemistry and Physics and Centre for Material Science at the Queensland University of Technology, (QUT), Australia. He is serving as an Associate Editor of the journal Flexible and Printed Electronics and Material Research Express (Institute of Physics, London). Recently, he has been elected as a Fellow of the Royal Chemical Society (FRSC) and a Foreign Fellow of the Maharashtra Academy of Sciences (FFMAS). He is a recipient of the Award for Excellence-Impact and Translation (2020), from the Centre for Materials Science, QUT, Australia, and the Vice-Chancellors Performance Award from QUT Australia (2016). He also received Thiemann Exchange Program Award from Technion-Israel Institute of Technology (2017), Israel, and the Foreign Collaborator Award from Grant-in-Aid for Scientific Research on Innovative Areas, MEXT, (2016) Japan. He has published 225 peer-reviewed research papers (H-index-51, close to 10,000 citations) and filed 3 US patents. Prof. Sonar delivered 90 invited talks at international conferences and institutes.

Talk Title: Molecular Engineering of π-Functional Conjugated Materials for Photonics, Electronics, and Sensing

Abstract: Next generation active electronic materials used in devices are undergoing continual improvements to generate devices that are high performance, lighter, flexible, stretchable, and more energy efficient with lower cost. Carbon based novel solution processable π-functional conjugated materials are the focus of intense academic and industrial research since they are important class of soft materials for large area electronics including transistors, displays, sensors and light harvesting devices. The active organic semiconducting materials are emerging due to their tunable light absorption/emission, interesting charge transport properties, relatively adequate HOMO-LUMO energies and ink formulation capability.
In my talk, I will explain the various classes of conjugated carbon-based materials either as polymers, small molecules or quantum dots prepared via chemically and electrochemically using various novel aromatic conjugated building blocks. In this presentation, the design, synthesis, optoelectronic properties, and device performance of novel advanced materials for field effect/electrochemical transistors, perovskite solar cells, light emitting diodes, optical sensors and various sensing devices will be discussed. Such materials and devices have great potential in future electronics, energy, health, and environmental monitoring.

Prof. Steven Ringel

The Ohio State University, USA

Bio: Steven A. Ringel is a professor and holds the Neal Smith Endowed Chair in the Department of Electrical and Computer Engineering at Ohio State. He is also the Founding Director of The Ohio State University Institute for Materials Research (IMR), which encompasses Ohio State’s multi-college materials research enterprise spanning 6 colleges, more than 140 faculty groups, and both government and industry-supported centers of research excellence. Prof. Ringel is an internationally recognized authority for his research innovation and leadership in electronic materials and devices, and particularly for his pioneering contributions that are advancing high efficiency and low-cost compound semiconductor-silicon integrated photovoltaics and also for his efforts to advance wide bandgap electronic and photonic device technologies through the development and application of several defect characterization methods.

Talk Title: Investigation and Comparison of Deep Acceptors in β-Ga2O3 using Defect Spectroscopies

Abstract: Steven A. Ringel(1), Hemant Ghadi(1), Joe F McGlone(1), Alexander Senckowski(2), Shivam Sharma(3), Man Hoi Wong(2) and Uttam Singisetti(3)
(1) Electrical and Computer Engineering, The Ohio State University, Columbus, Ohio,
(2) Electrical and Computer Engineering, University of Massachusetts Lowell, Massachusetts,
(3) Electrical Engineering, University of Buffalo, Buffalo, New York
Beta phase gallium oxide (β-Ga2O3) is a strong contender for next-generation high voltage and RF device applications. A key component of such devices is a semi-insulating, highly resistive buffer layer or substrate. To date, iron (Fe) has been the preferred acceptor impurity to achieve semi-insulating β-Ga2O3. Iron produces an energy level at EC-0.8 eV, which has been substantiated by theoretical and experimental studies and enables highly resistive material. However, it has also been shown that residual Fe impurities can result in device switching instabilities since the Fermi level can modulate the occupancy of the Fe trap state during standard biasing conditions. While progress to mitigate the impact of residual Fe impurities has occurred, there is also interest in exploring acceptors with much deeper energy levels to avoid device instabilities. Magnesium (Mg) and nitrogen (N) have emerged as candidates based on their predicted energy levels of EC-3.3 eV and EC-2.8 eV, respectively (H. Peelaers, et al., APL Mater. 7, 022519, 2019). This presentation will compare each acceptor, with a primary focus on N, using deep level optical spectroscopy (DLOS) and thermally based deep level transient spectroscopy (DLTS).
Here, N acceptors were introduced into HVPE-grown β-Ga2O3 by ion implantation. A uniform N-implantation profile was used targeting multiple doses in different samples, followed by an activation anneal. DLTS and DLOS measurements were applied before and after annealing. After implantation, multiple trap states appeared, most of which were removed by annealing, leaving a single, new state at EC-2.9 eV, with a Frank-Condon energy of 1.4 eV. The concentration of this state monotonically tracked with nitrogen concentration from SIMS. This energy level closely matches predicted values for an acceptor-like defect due to nitrogen atoms occupying the oxygen III sites, determined by density functional theory (DFT) calculations (H. Peelaers, et al., APL Mater. 7, 022519, 2019; Y.K. Frodason, et al. J. Appl. Phys. 127, 075701, 2020), The much deeper energy compared with Fe could imply a significantly lower operational instability than the shallower Fe acceptor at EC-0.8 eV. However, we found that the below midgap position of the NO(III) level, coupled with its small optical cross-section, complicates the trap concentration analysis by DLOS, which is important for understanding how to characterize very deep states in β-Ga2O3. Simultaneous hole emission to the valence band and electron emission to the conduction band was seen. Similar challenges might be present for Mg doping as well. The impact of this behavior on DLOS analysis is discussed, and a method to resolve this complication will be presented, which is needed to guide further optimization of this critical step in gallium oxide device development.

Dr. Harish Krishnaswamy

Sivers Semiconductors

Bio: Harish Krishnaswamy (Senior Member, IEEE) received the B.Tech. degree in electrical engineering from IIT Madras, Chennai, India, in 2001, and the M.S. and Ph.D. degrees in electrical engineering from the University of Southern California (USC), Los Angeles, CA, USA, in 2003 and 2009, respectively.,In 2009, he joined the Electrical Engineering Department, Columbia University, New York, NY, USA, where he is currently an Associate Professor and the Director of the Columbia High-Speed and Millimeter-Wave IC Laboratory (CoSMIC). In 2017, he co-founded MixComm Inc., Chatham, NJ, USA, a venture-backed startup, to commercialize CoSMIC Laboratory’s advanced wireless research. MixComm Inc. signed an agreement to be acquired by Sivers Semiconductor, Stockhom, Sweden, for $155M in October 2021. His research interests include integrated devices, circuits, and systems for a variety of RF, millimeter-wave (mmWave), and sub-mmWave applications.,Dr. Krishnaswamy has been a member of the Technical Program Committee of several conferences, including the IEEE International Solid-State Circuits Conference since 2015 and the IEEE Radio Frequency Integrated Circuits Symposium since 2013. He is a member of the DARPA Microelectronics Exploratory Council. He was a recipient of the IEEE International Solid-State Circuits Conference Lewis Winner Award for Outstanding Paper in 2007, the Best Thesis in Experimental Research Award from the USC Viterbi School of Engineering in 2009, the Defense Advanced Research Projects Agency Young Faculty Award in 2011, the 2014 IBM Faculty Award, the Best Demo Award at the 2017 IEEE International Solid-State Circuits Conference (ISSCC), the Best Student Paper Awards at the 2015, 2018, and 2020 IEEE Radio Frequency Integrated Circuits Symposium, the 2020 IEEE International Microwave Symposium, the 2021 IEEE MTT-S Microwave Magazine Best Paper Award, and the 2019 IEEE MTT-S Outstanding Young Engineer Award. He has served as a Distinguished Lecturer for the IEEE Solid-State Circuits Society.

Talk Title: Enabling Technologies for Low-Cost mmWave SATCOM Terminals

Abstract: mmWave 5G has received a lot of attention due to its ability to deliver extremely high data rates to the user, while also posing challenges to the designer related to the need for large-scale arrays, high-power and high-efficiency power amplifiers, and advanced mmWave packaging. However, over the past year or two, there has been a significant rise in the interest in mmWave SATCOM, driven by the lowering of the barrier to launch satellites into orbit. SATCOM ground terminals, however, pose challenges that are akin to those posed by 5G on steroids – the arrays are 10x larger in size, amplifier efficiency is even more important, <2dB LNA noise figure is required, and electromagnetic, mechanical and thermal packaging challenges are even more severe. This presentation will touch upon various enabling technologies for mmWave SATCOM ground terminals – RF-SOI technologies, high-power high-efficiency mmWave PA design, extremely-low-NF LNA design, and scalable multi-beamforming.

Prof. Ranjan Singh

NTU Singapore

Bio: Ranjan Singh is an Indian scientist and an Associate Professor at Nanyang Technological University (NTU) Singapore. He received B. Eng. in Telecommunications from Bangalore University (2001), M. Tech in Photonics from Cochin University (CUSAT), and a Ph. D. in Photonics from Oklahoma State University (2009). During 2009-2013, he was a postdoc at the Los Alamos National Laboratory. He founded TeraX Labs in 2013 at the Division of Physics, NTU Singapore. He is an elected fellow of OPTICA (OSA) for pioneering contributions in ultrafast terahertz photonics, active metamaterials, and sensors. His current research interests include terahertz electronic-photonic hybrid technologies for 6G communications, intelligent metasurfaces for beamforming, THz topological photonics, THz spintronics, quantum materials, and chalcogenide micro-nanophotonics. He has raised US$ 12M in competitive research grants, including a US $7M to develop on-chip terahertz topological photonics for 6G communication (TERACOMM). He has been listed as one of the top 1% of highly cited researchers by the web of science in 2020 and 2022.

Talk Title: Terahertz Silicon Topological Photonics for 6G communications

Abstract: Global digitalization and the recent rise of artificial intelligence-based data-driven applications have directed their vectors towards terabits per second (Tbps) communication links. The fast-evolving 5G communication network cannot fulfill this demand due to several technological challenges, including bandwidth scarcity, which has stimulated innovative technologies with a vision of 6G communication. Terahertz (THz) technologies have been identified as a critical candidate for the emerging 6G communication with the potential to provide ubiquitous connectivity and remove the barrier between the physical, digital, and biological worlds. Nonetheless, the existing THz photonic on-chip communication devices suffer from backscattering, bending loss, limited data speed, and lack of active tunability. Here, I will describe a new class of on-chip THz photonic topological devices consisting of low-loss, broadband single channel 160 Gbit/s communication link and critically coupled high-Q (Q ~ 106) cavities built on Silicon Valley-Hall Photonic Crystal. Silicon topological photonics will pave the path for augmentation of CMOS-compatible hybrid electronic-photonic driven terahertz technologies, vital for accelerating the development of 6G communications that would empower societies with real-time terabits per second wireless connectivity for network sensing, holographic communication, cognitive internet of everything, and massive digital cloning of the physical and the biological world.

Prof. Kaushik Basu

Indian Institute of Science

Bio: Kaushik Basu received the BE. Degree from the Bengal Engineering and Science University, Shibpore, India, in 2003, the M.S. degree in electrical engineering from the Indian Institute of Science, Bangalore, India, in 2005, and the PhD degree in electrical engineering from the University of Minnesota, Minneapolis, in 2012, respectively. He was a Design Engineer with Cold Watt India in 2006 and an Electronics and Control Engineer with Dynapower Corporation USA from 2013-to 15. He is an Associate Professor in the Department of Electrical Engineering at the Indian Institute of Science. He served as the Technical Program Committee Vice-Chair of IEEE ECCE 2019 and 2022. In 2019, he received the Prof. Priti Shankar Teaching Award from IISc. As a co-author, he received the Second Best Prize Paper Award from IEEE Transactions on Transportation Electrification in 2021. He is IEEE senior member and is the founding chair of both IEEE PELS and IES Bangalore Chapter. He is an Associate Editor of IEEE Transactions on Power Electronics and IEEE Transactions on Industrial Electronics. His research interests include most aspects of Power Electronic converter design from a few kW to a few MW for applications ranging from space, grid integration of renewables and storage to fast charging of electric vehicles.

Talk Title: Characterisation and Modelling of the Switching transitions of WBG Devices

Abstract: Silicon Carbide MOSFETs (SiC MOSFETs) fall into the class of wide band gap (WBG) power devices. These devices are commercially available in the voltage range of 600-3300V and compete with the state-of-the-art Si-insulated gate bipolar junction transistors (IGBTs). Superior material properties of SiC MOSFET lead to smaller die sizes. This results in faster switching transients and lower switching loss. However, it excites device and circuit parasitic that may lead to prolonged oscillation, high device stress, spurious turn-on and EMI-related issues. So, the benefit of using SiC MOSFET as a power device comes with numerous design challenges resulting in slow commercial adaptation. It is predicted that the overall market share of WBG devices (SiC and GaN together) will be roughly 10% of the total market for power semiconductors by 2025. To overcome the design challenges and fully utilise the benefits of fast-switching SiC MOSFETs, a better understanding of switching dynamics is essential. However, the switching dynamics of SiC MOSFET are different compared to its Si counterpart due to the highly non-linear device characteristics and participation of circuit parasitic in the process. In this talk, we will discuss our recent work on developing an analytical model of the switching dynamics for hard and soft transitions of SiC MOSFET by simplifying the complex non-linear dynamics predicted by the behavioural model. The developed model, given the device-related parameters extracted from the data sheet, estimated or measured circuit parasitic, can predict lost switching energy, rate of change of device voltage etc., necessary for a successful power converter design through computation with sufficient accuracy.

Dr. Saptadeep Pal

Auradine Inc., USA

Bio: Saptadeep Pal is the Founding Principal Engineer at Auradine, Inc., a startup focused on building sustainable, scalable and secure hardware solutions for next-generation web applications. He helps define ultra-low power circuits and architecture solutions for highly energy-efficient hardware products at Auradine. He received the B.Tech. degree in electrical engineering from IIT Patna, Patna, India, in 2015 and the M.S. and PhD degrees in Computer Engineering from the University of California at Los Angeles, CA, USA, in 2017 and 2021 respectively. His research at UCLA was focused on design and architecture of packageless and wafer-scale processor systems based on novel high-performance interconnect fabrics.

Talk Title: Waferscale Computing

Abstract: Fueled by the tremendous growth of new applications in the domain of big-data computing, deep learning, and scientific computing, the demand for increasing system performance is far outpacing the capability of conventional methods for performance scaling. Traditionally, performance and energy scaling has relied on transistor and silicon scaling. However, developing chips, often very large ones in the advanced technology nodes, is becoming very challenging and costly. Moreover, system performance is often limited by inter-die connections. Today, dies with different functionality are packaged and integrated using PCBs. Unlike silicon features, package and PCB features have barely scaled (about 4-5x) over the past few decades. This severely limits performance and efficiency of processor systems. Traditional scale-out system building, and integration methodologies are failing to deliver the performance today’s applications (such as artificial intelligence, big-data processing etc.) demand. As a consequence, future performance, power, and cost improvements cannot come from transistor technology alone. Then, how do we enable “System scaling”?

To target scale-out systems, we propose chiplet-based waferscale processors to dramatically reduce inter-die communication overheads. To that end, we developed the Si-IF technology where bare dies can be tightly integrated on a waferscale interconnect substrate to build scale-out processors up to a size of an entire wafer. However, building such a large consolidated waferscale system has its own challenges. For the first time, we explored the design space of waferscale power-delivery networks, cooling and trade-offs of yield and inter-GPM network topologies, etc. I will discuss some of these challenges and solutions that we developed to architect a large shared memory waferscale prototype system. Next, I will make a case for waferscale GPU and waferscale graph acceleration, where we leverage the massive bisection bandwidth and sub-1ns inter-die latencies to build high-performance computing systems. Our work shows that massive gains in excess of 5-10x can be achieved in terms of both performance gains as well as system energy using waferscale integration.

Dr. Meena Mishra

DRDO,INDIA

Bio: I have been serving in DRDO since 1989. My core area of research is RF Circuit Design and Characterisation along with high frequency and high power device design. I have Developed the small signal, nonlinear and noise models for high frequency devices like MESFET,HEMTand PHEMT. Developed design kits for the in-house developed devices. Designed and fabricated MIC low noise amplifiers with less than 1dB Noise Figure and high power amplifiers with power output of 1.5 kiloWatt.Presently working on design of GaN HEMT based MMIC and development of high power GaN MMIC technology.Main area of interest is in RF Characterisation ,modeling of low noise and high power
HEMTs and MMIC design.Presently working as Technology director on various state of the art projects. Successfully designed and developed GaN based wideband and narrowband Fr
MMIC power amplifiers, low noise amplifiers ,SPDT switch and multifunction circuits in S,C,X and Ku bands.

Talk Title: Indigenous GaN MMIC Technology

Abstract: Future trends for next generation strategic systems require multifunctionality and modularity like combining radar, communications, and electronic warfare in one system. This higher level of functional integration improves system performance through heightened awareness, improved responsiveness, and mission execution. The use of gallium nitride (GaN) MMIC as key component enables higher performance of systems meeting the requirements in small size with high power and hence GaN MMIC are emerging as an alternative or replacement for laterally diffused MOSFET (LDMOS) components. In most of next generation systems GaN MMIC technology is being considered because of high power density, high efficiency, wide bandwidth, and exceptionally long life. GaN on SiC has superior properties like higher breakdown voltage; higher saturated electron drift velocity and higher thermal conductivity. Hence GaN HEMTs also offer greater power density and wider bandwidths compared to Si; GaAs; and GaN on Si transistors. As shorter gate length GaAs and GaN transistors become available, coupled with improved circuit design techniques, new devices are becoming available that can perform comfortably to millimeter wave frequencies, opening new applications that were hard to contemplate a decade ago. This paper will briefly describe the indigenous GaN semiconductor technology that is enabling these developments to achieve optimum performance of devices, circuits and subsystems based on this technology.

Prof. Merlyne De Souza

The University of Sheffield

Bio: Merlyne De Souza received her PhD from the University of Cambridge in 1994. She was appointed Professor of Electronics and Materials at De Montfort University in 2003 and Professor of Microelectronics at the University of Sheffield in 2007. She has been a technical committee member of the IEDM (2012-2017) and IRPS (2003-2013). She has co-authored over 200 articles to date and is a distinguished lecturer and VP of membership of the IEEE Electron Device Society.

Talk Title: Revisiting doping mechanisms in a mixed electronic-ionic conductor PEDOT:PSS

Abstract: The mechanism of doping and de-doping in conjugated polymers such as PEDOT:PSS has been widely discussed on account of their application in bioelectronics from electrochemical batteries/supercapacitors to neural electrodes and transducers. In a conventional theory, there are three expected mechanisms of doping (i) Capacitive, leading to box shaped CV characteristics, whereby electrical double layers are formed at the surface of the polymer and the counter-electrode. This type of a film shows a capacitance independent of thickness. (ii) Faradaic, in which under positive bias, holes move towards the counter-electrode and react with species in the electrolyte leading to redox peaks in the cyclic voltammetry and (iii) Volumetric electrochemical doping, which is a combination of the above two, caused largely by cation injection into the bulk of the film, leading to electronic-ionic coupling of the holes and cations [1-3].
We demonstrate that the doping mechanism of K+ in PEDOT:PSS is more complex than these simple scenarios. Our films are able to retain more ions in a Faradaic reaction than via purely capacitive doping, pointing to coupling between the sulfonate anion and cation.
References:-
1.Exploiting mixed conducting polymers in organic and bioelectronic devices, Scott Keene et al Phys. Chem. Chem. Phys., 2022, 24, 19144
2. Understanding Volumetric Capacitance in Conducting Polymers, Christopher M Procter et al, Journal of Polymer Science, Part B: Polymer Physics 2016, 54, 1433-1436.
3. Berggren, M., Malliaras, G. G., (2019), How conducting polymer electrodes operate, Science, 364(6437), 233-234. https://doi.org/10.1126/science.aaw9295

Dr. Julien Ryckaert

imec, Belgium

Bio: Julien Ryckaert received the M.Sc. degree in electrical engineering from the University of Brussels (ULB), Belgium, in 2000 and the PhD degree from the Vrije Universiteit Brussel (VUB) in 2007. He joined imec as a mixed-signal designer in 2000 specializing in RF transceivers, ultra-low power circuit techniques and analog-to-digital converters. In 2010, he joined the process technology division in charge of design enablement for 3DIC technology. Since 2013, he is in charge of imec’s design- technology co-optimization (DTCO) platform for advanced CMOS technology nodes. In 2018, he became program director focusing on scaling beyond the 3nm technology node as well as the 3D scaling extensions of CMOS. Today, he is vice president logic in charge of compute scaling.

Talk Title: CMOS scaling: From Design into System Technology Co-Optimization

Abstract: Scaling is driven by the perspective of more function per unit cost. This paradigm has essentially been fueled with increasing transistor density by building ever more compact devices and finer interconnect capabilities. We are approaching records in feature sizes that starts questioning its viability moving forward. The entire Mendeleev table has been screened and manufacturing machines reach extreme levels in precision. However, an SoC is not composed of a monolithic set of functions, from compute blocks to memorization very different functions are expected from CMOS devices, not to mention the whole infrastructure that wraps the system (power and clock distribution, short signal nets and long signal nets, IOs and PLLs,…). The SoC is a vastly heterogeneous system. In order to keep scaling system performance, technology will not need to embrace that heterogeneity and find ways to leverage unique technology capabilities that improve system performance. This can only go hand in hand with a revision of system design practices and introducing novel architectures. CMOS Scaling is entering the era of System-Technology Co-Optimization. We will be talking about concepts leaning in that direction, such as backside processing and bonding technologies for smart partitioning, and extrapolate to the broader vision of the CMOS heterogeneous platform: CMOS 2.0.

Prof. M M Shaijumon

Indian Institute of Science Education & Research Thiruvananthapuram

Bio: Dr. Shaijumon is currently an Associate Professor at the School of Physics, IISER Thiruvananthapuram. He obtained his Ph.D. in Physics from Indian Institute of Technology Madras, India. Dr. Shaijumon’s research interests are in the area of nanomaterials and energy storage and conversion, focusing on the synthesis of novel nanostructures, design and development of efficient energy storage devices such as rechargeable batteries and supercapacitors, mostly looking at the materials science and physics of these systems. He received the DAE Young Scientist Research Award in 2012. He is also a recipient of the MRSI medal for 2019.

Talk Title: Engineered Carbon Materials for Sodium Ion Hybrid Capacitors

Abstract: Carbon materials, including carbon dots, carbon nanotubes, graphene, graphite, hard carbon, etc., have received greater attention due to their diversity, abundance, and favourable properties. The properties of carbon materials are easily tunable by doping with other elements or making composites with other materials.1 The unique chemical and structural features allow the possibility of engineering these materials, thus offering them unlimited advanced applications in energy storage and conversion.2 Here, efficient strategies to synthesise porous and hard carbon materials with significantly improved surface area and porosity features are explored for their applications in hybrid ion capacitors (HICs).3 For instance, engineered carbon samples with ‘open’ and ‘closed’ pores are synthesised to explore the sodium charge storage mechanism in hard carbon anodes. In-depth studies using different physicochemical techniques revealed strong evidence for adsorption/insertion-pore filling mechanism.4 The talk will also highlight our recent efforts on mass balancing of hybrid ion capacitor electrodes that could be employed as a design tool to guide the selection of optimized HIC devices for the intended applications.5

References

1. Choi, C. H., Park, S. H., Woo, S. I. ACS Nano 2012, 6, 7084–7091.

2. Liu W., Jiang H.and Yu H., Energy Environ. Sci., 2019, 12, 1751-1779.

3. Surendran, V., Arya, R. S., Vineesh, T. V., Babu, B., Shaijumon, M. M. J. Energy Storage 2021, 35, 102340.

4. Surendran V., Hema H. R., MS Oliyantakath Hassan, Vijayan Vinesh, Shaijumon, M. M, 2022, Batteries & Supercaps 2022, e202200316

5. Surendran, V., Lal, A., Shaijumon, M. M. ACS Appl. Mater. Interfaces 2021, 13 (44), 52610–52619.

Prof. Saptarshi Das

Penn State University, USA

Bio: Dr. Das received his B.Eng. degree (2007) in Electronics and Telecommunication Engineering from Jadavpur University, India, and Ph.D. degree (2013) in Electrical and Computer Engineering from Purdue University. He worked at Argonne National Laboratory (ANL) during 2013-2015. Dr. Das joined the Department of Engineering Science and Mechanics (ESM) at Penn State in January 2016. Dr. Das is the recipient of Young Investigator Award from the United States Air Force Office of Scientific Research and National Science Foundation (NSF) CAREER award. Das Research Group works on 2D materials for biomimetic sensing, neuromorphic computing, and hardware security applications

Talk Title: An insect-inspired collision detector based on atomically thin and light-sensitive 2D memtransistors

Abstract: Collision detection under poor illumination and nightly conditions pose significant challenge for manned and unmanned vehicles, flying drones, and robots navigating complex terrestrial and extraterrestrial geographies. Existing night vision cameras offer solution based on sophisticated enhancement algorithms or additional thermal sensors necessitating extensive and expensive hardware, which make them power-hungry and untenable for deployment in remote and resource constrained locations. In contrast, nocturnal flying insects can avoid collision using very limited neural resources. Insect-inspired collision detectors based on silicon complementary metal oxide semiconductor technology and field programmable gate arrays also exist, however, the physical separation between sensing and compute and absence of spike-based information processing capability increases their area and energy overhead. Here, we introduce an insect-inspired, spike-based, and in-sensor collision detector using a reconfigurable optoelectronic integrated circuit constructed based on atomically-thin and light-sensitive memtransistors. We imitate the escape response of lobula giant movement detector (LGMD) neuron found in many insect species and demonstrate timely collision detection for various real-life scenarios at night involving cars on collision course. Our collision detector has a small effective footprint of 40 µm2 and consumes miniscule energy of few hundreds pico-Joules.

Dr. Sai Gautam Gopalakrishnan

Indian Institute of Science, India

Bio: Sai Gautam Gopalakrishnan is an Assistant Professor at the Department of Materials Engineering, Indian Institute of Science since July 2020. After completing his dual degree (B. Tech.+M. Tech.) in Metallurgical and Materials Engineering, Indian Institute of Technology Madras (IITM) in 2013, he pursued his Ph.D. at the Massachusetts Institute of Technology (MIT) in Materials Science and Engineering under the guidance of Prof. Gerbrand Ceder. After graduating with his Ph.D. in June 2017, he subsequently pursued postdoctoral research under the mentorship of Prof. Emily A. Carter in Mechanical and Aerospace Engineering, Princeton University. Sai’s research group focusses on using density functional theory calculations and machine learning tools to study and discover materials for energy storage and energy harvesting applications. Some of his accolades include being selected as an “Associate” by the Indian Academy of Sciences in 2022, the “Best Ph.D. thesis” at MIT and the “Srinivasan Memorial Prize” for best academic performance at IITM.

Talk Title: Role of exchange-correlation functionals in migration barrier predictions

Abstract: A critical factor that influences the rate performance of batteries is the diffusion of the electroactive ions in the active materials, i.e., solid electrodes and/or electrolytes, which in turn is largely influenced by the ionic migration barriers (Em) within host frameworks. Determining Em precisely using experimental techniques, such as electrochemical impedance, variable temperature nuclear magnetic resonance, etc. is not a trivial task. Computationally, evaluating Em is often done via density functional theory (DFT)-based nudged elastic band (NEB) calculations or ab initio molecular dynamics (AIMD) simulations. Typically, DFT-NEB can yield a direct estimate of Em in a given material, while AIMD relies on statistical sampling of migration events (which becomes more difficult with increasing Em values). Hence, DFT-NEB is the preferred computational choice to determine Em. However, the accuracy of DFT-NEB calculations in estimating Em is dependent on the choice of exchange-correlation (XC) functionals, and the errors associated with using different XC frameworks has not been accurately quantified yet. Hence, in the first part of my talk, I will focus on assessing the accuracy of different XC frameworks (versus experiments) in estimating Em in a wide variety of electrode and solid electrolyte materials. Importantly, we find that the strongly constrained and appropriately normed functional yields better accuracy of Em on average, albeit with significant convergence difficulties and notable exceptions of high inaccuracy, while the generalised gradient approximation provides robust qualitative trends in its Em predictions. I will also discuss about the role of uniform background charge and the climbing image approximation in Em predictions.

Dr. Madhur Bobde

Alpha & Omega Semiconductor

Bio: Dr. Madhur Bobde received his Bachelors and Master’s degree (Integrated) from the Indian Institute of Technology, Bombay and his PhD. from North Carolina State University, USA

He is currently employed with Alpha & Omega Semiconductor as Chief Technology Officer. He has 25+ years of experience in the field of Power Semiconductors including Advanced Silicon power devices, Wide Band-Gap devices, process technology, packages & power modules and power management ICs.

He holds more than 150 US granted patents with several pending & publications in power semiconductor conferences and journals. He has also given invited talks and taught short courses in conferences including ISPSD and SEMICON

Talk Title: Advances in Silicon Power Semiconductor Devices

Abstract: Silicon power MOSFETs have made tremendous advancements in the past decade. The key concept that has led to this is that of charge balance. In conventional power MOSFET device the maximum doping level and the thickness of the drift region is limited by blocking voltage constraints and a triangular electric field results in its sub-optimal utilization.
The concept of charge balance involves adding an opposite polarity of charge in the drift region compared to default doping to modify the shape of electric field from triangular to trapezoidal for better utilization of drift region for voltage blocking, and allow significantly higher doping concentration for lower conduction losses. For low voltages (below 400V) the popular device structure to achieve this is the Split Gate Transistor (SGT). This device utilizes trench MOS charge balance with a shield electrode under the gate. In addition to significantly improving the On Resistance per unit area (~3x for 100V blocking), the shield electrode also significantly reduced the gate to drain miller capacitance (Crss) and Crss/Ciss ratio to allow for high frequency switching.
For high voltages above 400V, the depth of trench and thickness of liner oxide make SGT device impractical to fabricate. As a result, the Super-Junction transistor has emerged as the most successful MOSFET for high voltages. This device utilizes alternating P and N columns in the drift region thereby creating a charge balance. Methods such as multi epi, deep trench and fill have been demonstrated and are commercially successful for making superjunction transistors. These can achieve an On-Resistance reduction of up to 8x compared to planar DMOS transistor. However, presence of alternating P and N columns also results in peculiar Capacitance curves, particularly the Crss which drops sharply at low drain biases and then increases at higher drain biases. It also exhibits snappy diode reverse recovery.
Charge balanced structure is also finding use in bipolar devices such as IGBT and Fast recovery diodes. In these devices, charge balance is used for various performance enhancements such as improving turn-off losses, injection enhancement, and controlling injection efficiency for faster switching.
The goal of this seminar is to understand the device physics and electrical characteristics of charge balanced devices in unipolar and bipolar power devices. This seminar is intended for intermediate level audience.

Registration is OPEN ! Click Here

Registration Cost

Standard Pass

Standard Pass

Standard Pass

Important Dates

Submission Closes

Acceptance of Oral and Poster Papers

Full Length Paper Submission and Copyright Transfer Deadline

Technical Program Announcement

​Author and Speaker Registration Deadline

Early Bird Registration Deadline

Conference

Registration Form

Submit Online

Abstract

Full Paper

Prof. Prashant Murlidhar Sonar

Queensland University of Technology

Prof. Shreepad Karmalkar

IIT Bhubaneswar (at the time of presentation)

Prof. Shankar Kumar Selvaraja

Indian Institute of Science

Prof. Steven Ringel

The Ohio State University, USA

Dr. Anton Devillier

Tokyo Electron Ltd; USA

Dr. Abhinav Kandala

IBM Quantum, USA

Dr. Dhananjaya Dendukuri

Achira Labs, India

Dr. Seena V

Indian Institute of Space Science and Technology (IIST), India

Dr. Duvvuri satyanarayana Prasad

Centre for Materials for Electronics Technology (C-MET), Hyderabad, India

Prof. Doron Naveh

Bar-Ilan University, Israel

Prof. Sukomal Dey

Indian Institute of Technology Palakkad

Prof. Satyabrata Jit

Indian Institute of Technology (BHU) Varanasi, INDIA

Dr. Swaroop Ganguly

IIT Bombay, India

Dr. Dinesh Kabra

Indian Institute of Technology Bombay, India

Dr. Soumya Shubhra Nag

Indian Institute of Technology Delhi

Dr. Raghvendra Sahai Saxena

Solid State Physics Laboratory (DRDO), Delhi, India

Prof. Nicolas Volet

UV Medico, Denmark

Prof. Shankar Ekkanath Madathil

University of Sheffield

Prof. Siddharth Rajan

The Ohio State University

Dr. Harish Krishnaswamy

Sivers Semiconductors

Dr. Amit Ranjan Trivedi

University of Illinois at Chicago

Dr. Ananth Sundaram

Globalfoundries India Pte Ltd

Dr. Somu Ghosh

Texas Instruments, India

Dr. Prasanna Rajagopal

Texas Instruments, Bangalore

Dr. Ruchir Dixit

Siemens, India

Dr. Vinayak Bharat Naik

TECHNOLOGY DEVELOPMENT, GLOBALFOUNDRIES, SINGAPORE

Dr. Rwik Sengupta

Cadence, United States

Dr. Amitava Das

Tagore Technology Inc

Prof. Bent Weber

Nanyang Technological University

Dr. Ajay Kumar Vaidhyanathan

Intel/ India

Prof. Arindam Ghosh

Indian Institute of Science

Prof. Ranjan Singh

Author and Speaker Registration Deadline