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  • icee.ieee@iisc.ac.in

Prof. Prashant Murlidhar Sonar

Queensland University of Technology

Bio: Prof. Prashant Sonar is an ARC Future Fellow and Professor in the School of Chemistry and Physics and Centre for Material Science at the Queensland University of Technology, (QUT), Australia. He is serving as an Associate Editor of the journal Flexible and Printed Electronics and Material Research Express (Institute of Physics, London). Recently, he has been elected as a Fellow of the Royal Chemical Society (FRSC) and a Foreign Fellow of the Maharashtra Academy of Sciences (FFMAS). He is a recipient of the Award for Excellence-Impact and Translation (2020), from the Centre for Materials Science, QUT, Australia, and the Vice-Chancellors Performance Award from QUT Australia (2016). He also received Thiemann Exchange Program Award from Technion-Israel Institute of Technology (2017), Israel, and the Foreign Collaborator Award from Grant-in-Aid for Scientific Research on Innovative Areas, MEXT, (2016) Japan. He has published 225 peer-reviewed research papers (H-index-51, close to 10,000 citations) and filed 3 US patents. Prof. Sonar delivered 90 invited talks at international conferences and institutes.

Talk Title:  Molecular Engineering of π-Functional Conjugated Materials for Photonics, Electronics, and Sensing

Abstract: Next generation active electronic materials used in devices are undergoing continual improvements to generate devices that are high performance, lighter, flexible, stretchable, and more energy efficient with lower cost. Carbon based novel solution processable π-functional conjugated materials are the focus of intense academic and industrial research since they are important class of soft materials for large area electronics including transistors, displays, sensors and light harvesting devices. The active organic semiconducting materials are emerging due to their tunable light absorption/emission, interesting charge transport properties, relatively adequate HOMO-LUMO energies and ink formulation capability.
In my talk, I will explain the various classes of conjugated carbon-based materials either as polymers, small molecules or quantum dots prepared via chemically and electrochemically using various novel aromatic conjugated building blocks. In this presentation, the design, synthesis, optoelectronic properties, and device performance of novel advanced materials for field effect/electrochemical transistors, perovskite solar cells, light emitting diodes, optical sensors and various sensing devices will be discussed. Such materials and devices have great potential in future electronics, energy, health, and environmental monitoring.

Prof. Shreepad Karmalkar

IIT Bhubaneswar (at the time of presentation)

Bio: Shreepad Karmalkar is a Professor of Electrical Engineering at IIT Madras. He received the B. Tech and accelerated PhD degrees in Electrical Engineering from IITM, in 1983 and 1989, respectively. His interests are semiconductor devices and education. His recent devices related research has focused on modeling and simulation of power devices, nano-devices, GaN HEMTs and solar cells. He has developed popular online video courses on Solid State Devices, Semiconductor Device Modeling and Introduction to Research. 

Talk Title: Modeling and Design of Superjunctions in Silicon Carbide

Abstract: Superjunctions yield a lower specific on-resistance, RONSP, for a given breakdown voltage, than conventional p-n junctions. We derive (a) a new theoretical lower limit of RONSP for an ideal balanced superjunction that is 30 % lower than prior works, (b) closed-form design equations for a practical superjunction considering process variations for the first time, and show that the optimum p-pillar aspect ratio is < 15 whereas prior works have tried raising this ratio beyond 25. We also propose charge sheet superjunction as a viable alternative to superjunction in SiC material to avoid complexities associated with fabrication of p-pillars in SiC.

Prof. Shankar Kumar Selvaraja

Indian Institute of Science

Bio: Professor Shankar Kumar Selvaraja is Prof. RamakrishnaRao chair associate professor at CeNSE, IISc Banglaore. He is the current Chair of the National Nano fabrication Centre (NNfC) at IISc. Before joining IISc, he was with imec Belgium. His current area of research includes silicon photonic IC enabled optical connectivity technology, integrated photonic based sensors, neuromorphic photonics and quantum photonic integrated circuit. He has published over 250 research articles in international journals and conferences and has six international patents.

Talk Title: Silicon and silicon nitride photonics for sensing and communicaiton 

Abstract: In this talk, we shall discuss the strategies to integrate silicon and silicon nitride to create a broadband photonics platform. We shall discuss material requirement, device design, fabrication challenges and measurement results of detectors for potential sensor and high-speed communication applications. 

Prof. Steven Ringel

The Ohio State University, USA

Bio: Steven A. Ringel is a professor and holds the Neal Smith Endowed Chair in the Department of Electrical and Computer Engineering at Ohio State. He is also the Founding Director of The Ohio State University Institute for Materials Research (IMR), which encompasses Ohio State’s multi-college materials research enterprise spanning 6 colleges, more than 140 faculty groups, and both government and industry-supported centers of research excellence. Prof. Ringel is an internationally recognized authority for his research innovation and leadership in electronic materials and devices, and particularly for his pioneering contributions that are advancing high efficiency and low-cost compound semiconductor-silicon integrated photovoltaics and also for his efforts to advance wide bandgap electronic and photonic device technologies through the development and application of several defect characterization methods.

Talk Title: Investigation and Comparison of Deep Acceptors in β-Ga2O3 using Defect Spectroscopies

Abstract: Steven A. Ringel(1), Hemant Ghadi(1), Joe F McGlone(1), Alexander Senckowski(2), Shivam Sharma(3), Man Hoi Wong(2) and Uttam Singisetti(3)
(1) Electrical and Computer Engineering, The Ohio State University, Columbus, Ohio,
(2) Electrical and Computer Engineering, University of Massachusetts Lowell, Massachusetts,
(3) Electrical Engineering, University of Buffalo, Buffalo, New York
Beta phase gallium oxide (β-Ga2O3) is a strong contender for next-generation high voltage and RF device applications. A key component of such devices is a semi-insulating, highly resistive buffer layer or substrate. To date, iron (Fe) has been the preferred acceptor impurity to achieve semi-insulating β-Ga2O3. Iron produces an energy level at EC-0.8 eV, which has been substantiated by theoretical and experimental studies and enables highly resistive material. However, it has also been shown that residual Fe impurities can result in device switching instabilities since the Fermi level can modulate the occupancy of the Fe trap state during standard biasing conditions. While progress to mitigate the impact of residual Fe impurities has occurred, there is also interest in exploring acceptors with much deeper energy levels to avoid device instabilities. Magnesium (Mg) and nitrogen (N) have emerged as candidates based on their predicted energy levels of EC-3.3 eV and EC-2.8 eV, respectively (H. Peelaers, et al., APL Mater. 7, 022519, 2019). This presentation will compare each acceptor, with a primary focus on N, using deep level optical spectroscopy (DLOS) and thermally based deep level transient spectroscopy (DLTS).
Here, N acceptors were introduced into HVPE-grown β-Ga2O3 by ion implantation. A uniform N-implantation profile was used targeting multiple doses in different samples, followed by an activation anneal. DLTS and DLOS measurements were applied before and after annealing. After implantation, multiple trap states appeared, most of which were removed by annealing, leaving a single, new state at EC-2.9 eV, with a Frank-Condon energy of 1.4 eV. The concentration of this state monotonically tracked with nitrogen concentration from SIMS. This energy level closely matches predicted values for an acceptor-like defect due to nitrogen atoms occupying the oxygen III sites, determined by density functional theory (DFT) calculations (H. Peelaers, et al., APL Mater. 7, 022519, 2019; Y.K. Frodason, et al. J. Appl. Phys. 127, 075701, 2020), The much deeper energy compared with Fe could imply a significantly lower operational instability than the shallower Fe acceptor at EC-0.8 eV. However, we found that the below midgap position of the NO(III) level, coupled with its small optical cross-section, complicates the trap concentration analysis by DLOS, which is important for understanding how to characterize very deep states in β-Ga2O3. Simultaneous hole emission to the valence band and electron emission to the conduction band was seen. Similar challenges might be present for Mg doping as well. The impact of this behavior on DLOS analysis is discussed, and a method to resolve this complication will be presented, which is needed to guide further optimization of this critical step in gallium oxide device development.

Dr. Anton Devillier

Tokyo Electron Ltd; USA

Bio: Anton, born in Oregon, moved to South Africa where he completed his undergraduate degree at the University of Cape Town. After returning to America, he completed his studies at the University of Oregon. He has many years of experience working for top companies along the way – starting at Hyundai Semiconductor, moving to Maxim, Cypress Semiconductor, and Micron, and now holds the position of VP of Patterning Technology at TEL. His work at TEL includes logic scaling analysis with the development of many scaling boosters and patterning strategies to extend scaling through integration.

Talk Title: Not given 

Abstract: Over the last 20years or so the industry scale path has seen many transitions to enable what each preceding generation of technology thought was impossible. New technology becomes possible with the addition of patterning techniques that help enable each generation of smaller designs. This talk will go through some of the enabling technologies and how the industry of chip making made breakthrough after breakthrough to truly enable parts to be printed at dimensions and geometries far more exotic than any could have imagined. We will take a look at the recent history of technology scaling enablers and how they shaped the industries roadmaps and understanding of scaling. 

Dr. Abhinav Kandala

IBM Quantum, USA

Bio: Dr. Abhinav Kandala is an experimental physicist and manages the Quantum capabilities and demonstrations group at IBM Quantum. At IBM, his research has spanned coherence and control of superconducting qubits, multi-qubit device characterization, and applications of near-term quantum computers. Abhinav received his B. Tech in Engineering Physics from IIT Bombay and a PhD in Physics from The Pennsylvania State University. In 2019, he was recognized as on one of 35 innovators under 35 by MIT Tech Review.

Talk Title: Error mitigation and the path to quantum advantage

Abstract: Quantum processors based on superconducting circuits have now reached a scale that is well beyond direct diagonalization. However, in the absence of fault tolerance, the central question is whether such noisy processors can provide useful computations. In this context, error mitigation techniques can provide access to noise-free observables even from today’s noisy processors. I will introduce these techniques, discuss the current state of quantum hardware and recent experimental results, and chart out an immediately accessible path to quantum computational advantage.

Dr. Dhananjaya Dendukuri

Achira Labs, India

Bio: Dhananjaya Dendukuri is Chief Executive Officer & Co-Founder of Achira Labs, a pioneering point-of-care technology company based out of Bangalore. Dhananjaya returned to India with his passion for engineering and the belief that technology development for underserved markets must be done locally. Starting from his early career experience as a lab scientist and R&D manager (with over 30 publications and 7 issued patents), he now has more than a decade of experience with the fund-raising, commercial, operational and regulatory aspects of building and taking diagnostic technologies to market. He received the National Technology Award for new technologies (biotechnology) in 2016 and MIT Technology Review’s prestigious TR35 awards in India for the work that was being done at Achira. Dhananjaya serves on the jury of the Infosys Prize and the X-prize for diagnostics. He received his PhD in Chemical Engineering from MIT, a MASC in Chemical Engineering from the University of Toronto and a B.Tech in Chemical Engineering from the Indian Institute of Technology, Madras.

Talk Title: Hydrogel based sensors for medical diagnostic applications

Abstract: Synthetically fabricated hydrogel particles are increasingly used for bio sensing applications. Newly developed techniques allow fabrication of hydrogels with different morphologies, spatially segregated functionalization and tuned material properties. Hydrogel sensors embedded inside microfluidic devices have a number of advantages including multiplexing, good stability and low non-specific binding. The talk will discuss hydrogel sensor capabilities on Achira’s point-of-care platform. 

Seena V

Dr. Seena V

Indian Institute of Space Science and Technology (IIST), India

Bio: Dr. Seena.V received Ph.D. from the IIT Bombay in 2011. She served as a faculty member at IIT Jodhpur and R& D Consultant for NanoSniff Technologies Pvt. Ltd., incubated at IIT Bombay partly based on her research contributions in Microcantilever sensors. She is currently an Associate Professor in the Dept. of Avionics, Indian Institute of Space Science and Technology (IIST). Her main research is in the area of MEMS and CMOS-MEMS integration and Nanomechanical Sensor Systems. She is a recipient of NASI Young Scientist Platinum Jubilee Award, Kerala State Young Scientist Award, SERB Women Excellence Award ,Award for Excellence in Ph.D Thesis, IIT Bombay” and IEI Young Engineer Award .

Talk Title: MEMS Physical Sensors with Integrated FET based Electromechanical Transduction

Abstract: MEMS sensors and devices have numerous applications spanning across consumer gadgets, automotive electronics, industrial medical, defence, aerospace etc. Despite the wide and increasing demands for MEMS-based devices such as sensors and actuators in diverse applications, unlike semiconductor technologies like CMOS/VLSI, the design and fabrication of MEMS/Microsystems is not fully standardized. Most of the commercially available MEMS sensors are based on passive transduction mechanisms such as capacitive or piezoresistive with inherent performance limitations. FET based active transduction schemes have the potential to overcome these limitations with ease in CMOS-MEMS integration as an additional merit. This talk would give a brief overview of our attempts towards indigenous development of MEMS physical sensors with FET based electromechanical transduction with scope for CMOS-MEMS integration. 

D S Prasad

Dr. Duvvuri satyanarayana Prasad

Centre for Materials for Electronics Technology (C-MET), Hyderabad, India

Bio: Dr D S Prasad, Ph.D in physics, working as scientist in a Research & Development organization C-MET, Govt. of India. He had 25 years of hands-on experience in the refining of materials to purities of 99.99% (4N) through 99.99999% (7N). Skilled with the related aspects of purification technology, material handling and purity verification. Currently, he is in-charge for the activity “Recycling of end- of life silicon-Solar PV modules” supported by MeitY, Govt. of India

Talk Title: A novel approach for recycling of waste silicon solar photovoltaic modules: A step to promote circular economy

Abstract: With the average lifespan of a solar module being 25-30 years, it is predicted that the cumulative waste generated globally would be around 78 million tonnes by 2050. Hence, developing a process for the recycling of this solar waste is crucial to prevent environmental pollution and to recover valuable materials. It is important that the end-of-life of solar modules should stay green to maintain the circular economy. Our work is focused on the recovery of valuable materials from spent crystalline silicon solar modules by a combination of physical, chemical, and thermal operations to de-laminate the modules and purify the materials. Through this process, an economically viable method was established to recover high pure silicon along with other components such as glass, copper etc.

Prof. Doron Naveh

Bar-Ilan University, Israel

Bio: Doron Naveh earned his BSc in Materials Engineering, as well as a BSc and MSc in Physics from Ben-Gurion University of the Negev, and his PhD in Computational Materials Science from the Weizmann Institute of Science. In 2008 he moved to Princeton University and in 2009 to Carnegie-Mellon University for post-doctoral fellowships, where he started the transition from computational to experimental sciences. In 2012 he started the 2D Materials & Devices Lab in the Bar-Ilan Facultyof Engineering, where he is now an Associate Professor.

Talk Title: From Enhanced Responsivity to Deep Sensing: Advances in Light Detection

Abstract: 

The emergence of 2D layered compounds has ameliorated the fields of electronic and optoelectronic devices and are considered as a promising platform for the developments of devices in the quantum era. To list a few examples, this progress has included the demonstrations of ultrafast photodetectors, room-temperature mid-infrared photodetection, and electrical tunable spectral response by Stark effect. In this talk the recent progress on combined trajectories will be discussed – including fast, room temperature short wave infrared detection of hot photo carriers by intercalated MoS2 and a few examples on the electrical control of spectral response in photodetectors of 2D materials and heterostructures. Finally, the use of computational resources for the performance of spectral measurements, termed “Deep Sensing”, will be shortly reviewed.

References

[1] A. Twitto et al. ACS Nano 2022 https://doi.org/10.1021/acsnano.2c07347

[2] C. Stern et al. Advanced Materials 2021 https://doi.org/10.1002/adma.202008779

[3] S. Yuan et al. Nature Photonics 2021 https://doi.org/10.1038/s41566-021-00787-x

Prof. Sukomal Dey

Indian Institute of Technology Palakkad

Bio: Sukomal Dey received Ph.D. degree from the Indian Institute of Technology Delhi, New Delhi, India, in July 2015. From August 2015 to July 2016, he was a Project Scientist with Industrial Research and Development Centre, IIT Delhi. From August 2016 to June 2018, he was with National Tsing Hua University, Taiwan, as a Post-doctorate Research Fellow. Since June 2018, he has been an Assistant Professor with the Department of Electrical Engineering, Indian Institute of Technology Palakkad, India. 

Talk Title: Radio Frequency Micromachined Devices and Circuits for Microwave to millimeter Wave Applications

Abstract: When radio frequency microelectromechanical system (RF MEMS) based switches appeared more than 25 years ago, micromechanics have attracted huge attention for enabling near-ideal microwave devices. Since then, MEMS switches and circuits went through different development stages and are currently proving themselves commercially. Micromachining technology has the potential to become an enabling technology for microwave, millimeterwave to even sub-millimeterwave systems. Although, reliability of MEMS devices is one of the prime challenge to meet present state-of-the-art performances due to occurrence of multiple failure modes after few cycles of operations. This reliability becomes more critical when multiple MEMS switches operate simultaneously like in a multi-bit digital phase shifters. First phase primarily concentrates on the reliability improvements on MEMS based switching networks and digital phase shifters. It takes multiple iterations and extensive characterizations to conclude with a reliable MEMS phase shifters. Second phase briefly presents development of tunable bandpass filters utilizing MEMS switches for present 5G applications. Third phase briefly shows the potential of micromachined antennas for phased array networks. Finally, present webinar concludes with current research activities of RF MEMS in sub-millimeterwave regime. 

Prof. Satyabrata Jit

Indian Institute of Technology (BHU) Varanasi, INDIA

Bio: Prof. S. Jit is a senior Professor in the Department of Electronics Engineering, Indian Institute of Technology (BHU) Varanasi, INDIA. He has supervised 31 Ph.D. theses and has published 198 journal articles (including 73 IEEE papers) and authored/coauthored/edited 06 books. Prof. Jit is an Editor of the IETE Journal of Research, Associate Editor of two journals: IET Micro & Nano Letters and Journal of Electronic Materials.

Talk Title: Modeling, simulation and applications of engineered TFETs

Abstract:  The tunnel field effect transistor (TFET) has drawn considerable attentions for future generation low-power VLSI/ULSI applications due to its extremely low sub-threshold current and good switching characteristics. The TFET possesses low sub-threshold swing below the Boltzmann limit of 60 mV/decade of the bulk MOSFETs. However, the major drawback of the TFET is its very poor ON current. Several techniques have been introduced to improve the performance of the TFETs through various structural modifications. The present talk will introduce the performance analysis of some engineered TFET structures via theoretical modelling and commercially available TCAD simulations. Finally, some applications of the engineered TFETs in the SRAM design and level-free bio-sensors will also be discussed.

Dr. Swaroop Ganguly

IIT Bombay, India

Bio: Swaroop Ganguly received the B.Tech. from IIT Kharagpur, and the Master’s and Ph.D. from UT Austin. He worked in R&D roles at Freescale, Tokyo Electron, and IMEC; has been a Visiting Scientist at IBM Research. At IIT Bombay, he is Institute Chair Professor, PI of the nanoelectronics center, and Professor-in-Charge of the Research Park. His interests are in semiconductor device physics and modeling. He has published over 180 papers in international peer-reviewed conferences and journals.

Talk Title: Multiphysics Modeling of Wide Bandgap Devices

Abstract:  The design and analysis of electronic devices increasingly demand ‘multi-physics’ modeling. In this context, that most commonly means we have to incorporate the physics of thermal, mechanical or other effects in additional to the usual, viz. electron transport plus electrostatics. In this talk, I will go through the following three case studies, drawn from our work, on multi-physics simulation of wide bandgap semiconductor devices. First, the effects of substrate thinning on GaN HEMT performance. Second, the incorporation of mechanical strain for performance enhancement in SiC power MOSFETs. And third, the electro-thermal modeling of their short-circuit capability.

Dr. Dinesh Kabra

Indian Institute of Technology Bombay, India

Bio: Dinesh Kabra is a photonics physicist at the Indian Institute of Technology Bombay. He is working with the next generation of optoelectronic materials for solar cells and display technologies. Prior to joining the IIT Bombay, he was Herchel Smith Fellow at Cavendish Laboratory, University of Cambridge, UK. He was also an honorary postdoctoral fellow at Trinity Hall College of University of Cambridge, UK. He did his PhD in Physics of materials from JNCASR, Bengaluru- India and Masters in Laser Science & Applications from Devi Ahilya University, Indore.

Talk Title: State of art TADF OLEDs Fabrication Cluster Tool with Novel Charge Transport Layers.

Abstract:  Organic light emitting diodes (OLEDs) have become a choice of light element for small area display devices and progressing for large area and lighting solutions. With advancement in emissive materials, a lot of emphasize is given to novel thermally activated delayed fluorescence (TADF) based compounds. In general, these devices are multilayer structure with typical thickness of layers in the range of 5nm – 30 nm and require a good control on uniformity and compactness. We developed an indigenous multi-chamber cluster tool to make state-of-art OLEDs, with semi-automation approach. I will share design and results of devices made using this tool which consists of novel charge transport layers for OLED structure with a promise of improved performance in terms of stability and reduced leakage currents.

Dr. Soumya Shubhra Nag

Indian Institute of Technology Delhi

Bio: Dr. Soumya joined the Department of Electrical Engineering, IIT-Delhi in September 2018. He works in power electronics in transportation electrification, DC distribution system, and renewable energy systems. Prior to joining IIT Delhi, he was working as a Research Fellow at the Rolls-Royce@NTU Corporate Lab, NTU, Singapore where he worked on high power battery chargers for marine and aerospace applications.
He obtained M.Tech, PhD degree from IIT-Kanpur and Bachelor of Electrical Engineering from Jadavpur University, Kolkata.

Talk Title: Advanced Power Devices Packaging

Abstract:  Si-MOSFET/IGBT finds wide application in personal computers, servers, micro-inverters, motor-drives, telecom systems, etc. Advent of WBG semiconductor technology has not been able to replace the Si Technology. However, due to the aggressive needs of the power management systems in terms of higher power-density, lower parasitic-inductance, lower thermal-resistance, Si semiconductor industry is still going through innovations to keep the performance of devices at optimum level.
Recent improvements in Si-device packaging technology have significantly optimized device parameters and figure-of-merits (RDS(ON)*Qg, Qrr, Esw). Furthermore, with the increase in system current requirements, optimization of these device parameters become important which resulted in advent of packages like DPAK, D2PAK, SO-8, CopperStrapTM SO-8, PowerPakTM, LFPAKTM, DirectFETTM, TOLL, sTOLL, etc. This talk will elaborate the evolution and trends in packaging technologies for achieving better device characteristics which can enable high performance product designs for automotive, energy, data center applications.

Dr. Raghvendra Sahai Saxena

Solid State Physics Laboratory (DRDO), Delhi, India

Bio: Raghvendra Sahai Saxena received his Ph.D. degree from IIT, Delhi, India in 2012. He is currently a Scientist with the Solid-State Physics Laboratory, DRDO, Delhi, India. He is an American Society for Quality certified Reliability Engineer. His current research interests include infrared detector material & device technologies, readout integrated circuits and power electronic devices. He has authored and co-authored more than hundred papers in international journals and conference proceedings in above fields.

Talk Title: Flip chip bonding of integrated circuits

Abstract:  Flip chip bonding is used to connect semiconductor devices, integrated circuits, micro-electro-mechanical systems (MEMS) etc. with external circuitry or another integrated circuit using metal bumps deposited on the chip pads. This technology is quite common in high density interconnections in mega pixel focal plane array sensors. It can be utilized for getting millions of connections among the cells of a power MOSFET using micro bump array. A method of estimating the interconnection yield and connection reliability using daisy chain and fanout pattern on transparent substrates has been implemented. The results have been used for analysis and optimization of flip chip process.

Prof. Nicolas Volet

UV Medico, Denmark

Bio: Nicolas Volet holds a PhD in laser physics from EPFL (Switzerland), after which he worked in Santa Barbara (CA, USA), first as a postdoc in silicon photonics at UCSB and later setting up an R&D center for a telecom company. He now heads a research group of Integrated Photonics at Aarhus University (Denmark) and is a Board Member of the Danish Optical Society. In 2020, he co-founded UV Medico, a company based in Aarhus with the mission to fight the spread of infectious diseases with human-safe UV light.

Talk Title: New market segments enabled by far-UVC technologies

Abstract:  Part of the ultraviolet spectrum from 200 nm to 230 nm wavelength, called far-UVC, is highly absorbed by proteins in the superficial inactive cells of the skin and eyes. This allows for direct exposure of far-UVC at effective doses for pathogen deactivation.
UV Medico develops and produces far-UVC solutions. Our products have the advantage of being suitable for continuous disinfection of both the air and surfaces in occupied spaces. As such, far-UVC has a broader application area than conventional germicidal UV light sources which damage living cells. The latter are restricted to applications without direct human exposure, such as upper room ventilation systems and disinfection robots.
Research on far-UVC has recently triggered a movement to increase exposure limits and adapt regulations accordingly. With the progressive adherence of regulatory agencies, new applications are enabled. This presentation will focus on the food industry as an example of the diverse application field.

Prof. Shankar Ekkanath Madathil

University of Sheffield

Bio: Prof Shankar Ekkanath Madathil @ EM Sankara Narayanan is presently a professor in power electronics systems. He was a Royal Society Industry Fellow in Rolls-Royce between 2013 and 2017 where he worked on the systems impact of next generation power electronics technologies; prior to that he was a Royal Academy of Engineering Chair in Power Electronics from 2007-2013. His team has proven world leading design-2-manufacture expertise in Silicon and GaN. He is an editor of IEEE – TDMR, IEEE-TED, and Proceedings of the Royal Society A and an associated editor of IET – PEL and holds 40 patents/applications and published more than 250 articles.

Talk Title: Options towards high frequency and high power density in Silicon MOS-Bipolar devices

Abstract:  Driven largely by the electrification of transport agenda, there is a major thrust world-wide to develop advanced power semiconductor device technologies in Wide Bandgap Semiconductor device technologies and in Silicon. This talk will primarily address key advances in Silicon MOS-Bipolar device technologies to achieve high frequency and high-power densities, to maintain its competitiveness against advances in SiC technologies.

Prof. Siddharth Rajan

The Ohio State University

Bio: Siddharth Rajan is Professor of Electrical and Computer Engineering, and Materials Science and Engineering departments at The Ohio State University, where he joined the faculty in 2008. He received his PhD in Electrical and Computer Engineering in 2006 from University of California, Santa Barbara, and has held research positions at UC Santa Barbara and GE Global Research.

Talk Title: Electrostatic Engineering for High-Performance Wide and Ultra-Wide Bandgap Electronic Devices

Abstract:  In this presentation, we will review recent work on the integration of high permittivity dielectrics with wide and and ultra-wide bandgap semiconductor devices to obtain improved high power and high frequency performance. 

Dr. Harish Krishnaswamy

Sivers Semiconductors

Bio: Harish Krishnaswamy (Senior Member, IEEE) received the B.Tech. degree in electrical engineering from IIT Madras, Chennai, India, in 2001, and the M.S. and Ph.D. degrees in electrical engineering from the University of Southern California (USC), Los Angeles, CA, USA, in 2003 and 2009, respectively.,In 2009, he joined the Electrical Engineering Department, Columbia University, New York, NY, USA, where he is currently an Associate Professor and the Director of the Columbia High-Speed and Millimeter-Wave IC Laboratory (CoSMIC). In 2017, he co-founded MixComm Inc., Chatham, NJ, USA, a venture-backed startup, to commercialize CoSMIC Laboratory’s advanced wireless research. MixComm Inc. signed an agreement to be acquired by Sivers Semiconductor, Stockhom, Sweden, for $155M in October 2021. His research interests include integrated devices, circuits, and systems for a variety of RF, millimeter-wave (mmWave), and sub-mmWave applications.,Dr. Krishnaswamy has been a member of the Technical Program Committee of several conferences, including the IEEE International Solid-State Circuits Conference since 2015 and the IEEE Radio Frequency Integrated Circuits Symposium since 2013. He is a member of the DARPA Microelectronics Exploratory Council. He was a recipient of the IEEE International Solid-State Circuits Conference Lewis Winner Award for Outstanding Paper in 2007, the Best Thesis in Experimental Research Award from the USC Viterbi School of Engineering in 2009, the Defense Advanced Research Projects Agency Young Faculty Award in 2011, the 2014 IBM Faculty Award, the Best Demo Award at the 2017 IEEE International Solid-State Circuits Conference (ISSCC), the Best Student Paper Awards at the 2015, 2018, and 2020 IEEE Radio Frequency Integrated Circuits Symposium, the 2020 IEEE International Microwave Symposium, the 2021 IEEE MTT-S Microwave Magazine Best Paper Award, and the 2019 IEEE MTT-S Outstanding Young Engineer Award. He has served as a Distinguished Lecturer for the IEEE Solid-State Circuits Society.

Talk Title: Enabling Technologies for Low-Cost mmWave SATCOM Terminals

Abstract:  mmWave 5G has received a lot of attention due to its ability to deliver extremely high data rates to the user, while also posing challenges to the designer related to the need for large-scale arrays, high-power and high-efficiency power amplifiers, and advanced mmWave packaging. However, over the past year or two, there has been a significant rise in the interest in mmWave SATCOM, driven by the lowering of the barrier to launch satellites into orbit. SATCOM ground terminals, however, pose challenges that are akin to those posed by 5G on steroids – the arrays are 10x larger in size, amplifier efficiency is even more important, <2dB LNA noise figure is required, and electromagnetic, mechanical and thermal packaging challenges are even more severe. This presentation will touch upon various enabling technologies for mmWave SATCOM ground terminals – RF-SOI technologies, high-power high-efficiency mmWave PA design, extremely-low-NF LNA design, and scalable multi-beamforming.

Dr. Amit Ranjan Trivedi

University of Illinois at Chicago

Bio: Amit is an associate professor in the department of electrical and computer engineering at University of Illinois at Chicago. His research interest is in low power computing, neuromorphic computing, and emerging technologies. He was awarded the IEEE Electron Device Society fellowship in 2014, where he was one of the three recipients worldwide. He was also awarded Sigma Xi Best Ph.D. thesis award at Georgia Tech. He has also received the NSF CAREER award and College of Engineering Faculty Research Award from UIC.

Talk Title: Two-Dimensional Material-based Higher-Order Neuromorphic Computing with Dynamic Weights

Abstract:  The increasing complexity of deep learning systems has pushed conventional computing technologies to their limits. While memristor is one of the prevailing technologies for deep learning acceleration, it is only suited for classical learning layers where two operands, namely weights and inputs, are processed at a time. Meanwhile, to improve the computational efficiency of deep learning for emerging applications, a variety of non-traditional layers, requiring concurrent processing of many operands, are becoming popular. For example, hypernetworks improve their predictive robustness by simultaneously processing weights and inputs against the application context. Two-electrode memristor grids cannot natively support such operations of emerging layers. Addressing the unmet need, this talk discusses two-dimensional material-based neuron and synapses that can be controlled by multiple gate terminals. Thus, exploiting crossbar’s gate controllability, multiple operands could be concurrently processed within the same crossbar. Many advanced inference architectures that can generalize beyond a typical passive crossbar thus become possible. Overall, the ultra-low-power, higher-order processing capacity of the discussed gate-tunable crossbars and neurons harnesses high robustness and efficiency of emerging deep learning layers within area/power-constrained devices such as mobile, sensor, and embedded systems.

Dr. Ananth Sundaram

Globalfoundries India Pte Ltd

Bio: Ananth has been working in Compact modeling for > 10 years and currently manages the RF FET device compact modeling team in India for Globalfoundries. His team’s experience and interaction with customers has enabled him and his team to understand customer requirements for RF design and resolve problems faced by the RF design community in the industry. 

Talk Title: RF Modeling challenges for emerging technologies

Abstract:  With both evolutionary and disruptive changes in standards for wireless communications, the prediction of device behavior under regular and extreme conditions has become critical for designers to get first time right products. It’s no longer enough to be accurate in current, voltage and transconductance predictions but it’s a need to predict non-linearities accurately as well. We will talk about some of these challenges in this talk.

Dr. Somu Ghosh

Texas Instruments, India

Bio: Somu Ghosh is an SMTS (Senior Member of Technical Staff) at Texas Instruments working in the Analog Technology Development department under the Technology Manufacturing Group. He leads development of software solutions, analytics and business dashboards to accelerate and monitor new technology development at TI in the areas of spice modelling, reliability modelling, technology transfer and PDK development. Across the last 17 years, he has worked in IP development & verification, product selection and software.

Talk Title: PDK Development – Philosophy and Best Practices

Abstract:  In an enterprise environment, designers consume and build on technology information using the Process Development Kit (PDK). In this tutorial we will cover the PDK development flow, consumables that go into the PDK and philosophy and design practices that are associated with building the PDK. This tutorial will give an umbrella view of the PDK and unique aspects of building PDK for different technologies.

Dr. Prasanna Rajagopal

Texas Instruments, Bangalore

Bio: PRASANNA RAJAGOPAL is applications engineer at Texas Instruments, Bangalore where he is supporting applications of High Voltage GaN devices in high power broad industrial projects. Before that, he worked as a Systems Engineer at TI, Dallas for 5 years where he was responsible for developing reference design solutions for Grid Infrastructure in Industrial Systems. Prasanna brings to this role his expertise in power electronics and mixed-signal systems. Prasanna earned his PhD from IISc, Bangalore, India in 2011.

Talk Title: Integrating silicon driver with GaN transistor simplifies power system design and enhances performance

Abstract:  GaN (Gallium Nitride) transistors can switch at much higher rate as compared to Silicon MOSFETs while bringing in advantages of lower switching losses and reduce system size. However, switching at higher slew rate poses challenges in terms of switching performance due to parasitic common-source inductances. This presentation talks about advantages of integrating silicon driver with the GaN FET in an integrated package to optimize the gate loop to enable excellent switching performance at slew rates above 100V/ns. In addition, the package integrates protection features like over current/short circuit protection and monitoring junction temperature to simplify power converter designs.

Dr. Ruchir Dixit

Siemens, India

Bio: Ruchir has close to 25 years of experience in the semiconductor industry focused having executed at multiple levels of responsibilities in design and development of ASIC, FPGA and PCB products. In all these years, Ruchir has either directly worked on or with customers on over 200 IC Tapeouts. After spending close to 10 years in the IC development roles, Ruchir moved into EDA and Applications. Over time Ruchir has held various leadership roles and has worked with many customers world-wide and helped them to define the problem and then work to create solutions.

Currently, Ruchir is the Treasurer and Executive Council Member of IESA (India Electronics & Semiconductor Association) and the Chairperson of the Bangalore Chapter of IESA. Ruchir is an intrinsic member of all key decision making bodies both at national & International levels. Ruchir moved to India in 2005 to start building the customer facing organization at Mentor. Ruchir is an alumnus of Wayne State University, Michigan and Haas School of Business at UC Berkeley.

Talk Title: Challenges in Electronic Design Automation in modern technologies

Abstract:  Challenges in Electronic Design Automation in modern technologies

Dr. Vinayak Bharat Naik

TECHNOLOGY DEVELOPMENT, GLOBALFOUNDRIES, SINGAPORE

Bio: In the on-going era of artificial intelligence, IoT and autonomous vehicles, the semiconductor industry has actively been developing emerging non-volatile memory (NVM) technologies. Spin-Transfer-Torque (STT-MRAM) technology has proven to be a viable NVM technology solution to replace embedded flash in advanced microcontroller and microprocessor units. In this talk, the status of 22FDX® embedded MRAM technology for industrial-grade MCU & IOT applications, the impact of RF interference on MRAM and vice-versa, and the potential of MRAM for next-generation high-performance memory applications will be presented.

Talk Title: Reliable STT-MRAM Technology for Advanced MCU & IOT Applications

Abstract:  In the on-going era of artificial intelligence, IoT and autonomous vehicles, the semiconductor industry has actively been developing emerging non-volatile memory (NVM) technologies. Spin-Transfer-Torque magnetic random access memory (STT-MRAM) technology has proven to be a viable NVM technology solution to replace embedded flash in advanced microcontroller and microprocessor units. In this talk, the status of 22FDX® embedded MRAM technology for industrial-grade MCU & IOT applications, the crosstalk between MRAM & RF in a single EMI chip, and the trade-offs among MTJ device performances to optimize MRAM reliability for next-generation memory applications will be presented.

Rwik Sengupta

Dr. Rwik Sengupta

Cadence, United States

Bio: Rwik is a Director of Physical Signoff Enablement, DTCO and Design Migration Teams in Cadence Design Systems. He is passionate about manufacturing technology breakthroughs and the impact it has on Design Optimization. He has previously worked at Samsung as a Director of R&D, leading DTCO activities for n+2 node pathfinding. Before that, he worked at ST Micro as a Design-Technology Interface, managing foundational and AMS IP design requirements and optimizations for n+1 nodes. 

Talk Title: DTCO: How the industry has evolved

Abstract:  Since 1965, when Gordon Moore made his now famous self-fulfilling prophecy, optical scaling and material systems enabled a direct 0.5x area scaling node over node, for the next 30 years or so. While in no way was this scaling straightforward i.e.: engineering Innovation was needed; We were not approaching physical limits of material systems or optical limits of the printing systems. As area scaled, device and parasitic capacitance scaled almost linearly, without appreciable increase in effective Resistance or Leakage currents. This fulfilled the conditions for Dennard’s Law, enabling a geometric shrink driven performance boost and power reduction. In the early 2000s, for the 32/28mm node the rules of engagement changed, driven primarily by increase in leakage. However, design was still somewhat isolated from the disruption by clever technology decisions. By the time the industry was developing the 22/16nm nodes in 2005, it was no longer possible to optimize technology alone due to limits of optical/patterning systems, and the term DTCO was coined. Since then, DTCO has evolved to design around patterning and integration challenges, determine device and interconnect choices to drive PPA as we push the physical electrical limits of semiconductor manufacturing. My talk will cover some interesting aspects of how DTCO has impacted Technology Definition since its conception in 2005 to current day.

Amitava - Amitava Das

Dr. Amitava Das

Tagore Technology Inc

Bio: Amitava Das is a co-founder of Tagore Technology. Tagore Technology’s products include power GaN as well as RF GaN devices and IC’s. Amitava obtained his Ph.D. in EE from Purdue University. Amitava spent 14 years at Motorola/Freescale working at various aspects of semiconductor technology such as fabrication, design and operations. Prior to joining Motorola, Amitava was an associate professor of EE at IIT-Bombay. 

Talk Title: Integration Choices in Power GaN HEMT 

Abstract:  Wide bandgap semiconductors, such as GaN, are winning designs in the power supply market. Power supply designers have multiple options, such as using standalone GaN FET, GaN FET with integrated driver or GaN FET power module. GaN FET with integrated driver can be monolithic or heterogenous integration of two die – a GaN die and a CMOS driver die. This talk will review various integration options and highlight tradeoffs between them

Bent Weber

Prof. Bent Weber

Nanyang Technological University

Bio: Weber is a Singapore National Research Foundation (NRF) Fellow and Nanyang Assistant Professor (NAP) at Nanyang Technological University (NTU). He obtained his PhD from the Centre for Quantum Computation and Communication Technology (CQC2T) at The University of New South Wales (UNSW) Sydney, Australia, where he developed atomic-scale silicon quantum devices by scanning tunnelling microscopy. Weber’s group at NTU investigates 2D and topological materials for their potential in quantum device applications.

Talk Title: Tunable Many-body Interactions and Induced Superconductivity in a Helical Luttinger Liquid

Abstract:  The interplay of topology, superconductivity, and many-body correlations in 1D has become a subject of intense research for the pursuit of non-trivial superconducting pairing. The boundaries of atomically-thin topological insulators in 2D – amongst them the quantum spin Hall (QSH) insulator – provide a natural realisation of strictly 1D electronic structure with linear (Dirac) dispersion and spin-momentum locking (helicity).
We show that the topological edge states of the QSH insulator 1T’-WTe2 harbour a strongly correlated 1D electronic ground state – a helical Tomonaga-Luttinger Liquid (TLL) – whose many-body Coulomb interactions can be effectively controlled by the edge state’s dielectric environment. This demonstrates tunability of a helical TLL in both its fundamental dependencies on potential and kinetic energy terms, respectively. Finally, we show that super-conductivity can be induced into the 1T’-WTe2 quantum spin Hall state by proximity-coupling to a superconducting van-der-Waals substrate, giving rise to an induced superconducting order parameter as large as 0.6meV in WTe2, stable beyond a B=2T magnetic field.

Ajaykumar Vaidhyanathan

Dr. Ajay Kumar Vaidhyanathan

Intel/ India

Bio: Ajay Kumar Vaidhyanathan is an Electromagnetics expert. At present he plays the role of a Senior Technologist on Package-Electricals for Graphics group. He has about 30 years of experience, with a Master’s Degree in Electronics. His expertise spans Signal Integrity, Power delivery, EMC, and Nanoscience.
He has been with Intel for the past 16+ years. He started at Intel with the Data Center Group, and, over the years, he has worked in different roles across different Bus. He established the EMC Test and Measurement capability in Bangalore.The EMC capability can cover 90% of tests required for EN, IEC, FCC standards.
He has 13 patents to his credit. Recently, he has been leading efforts to investigate a Graphene-based solution for EMI and Thermal performance improvements. Before joining Intel, Ajay was with Honeywell-UK, GE-USA, and Measurement Technology Limited, India. His professional journey, apart from Intel, has enabled him to work across Industrial, Automotive, and Aerospace Segments

Talk Title: The requirement for 2D functional materials to solve today’s challenging Engineering problems

Abstract:  At present we are facing insurmountable challenges in solving engineering issues in many engineering domains. For example, Thermal, Mechanical, EMI, Power integrity, signal integrity etc. The unique properties of 2D materials have the potential breakthrough solution in these engineering domains. Another advantage of this is we can modify their functional characteristics depending on our needs. One of the major challenges at present we are facing to adapt this technology, is due the challenges we face in High Volume Manufacturing. In this presentation I will be discussing the need, Examples of how we are trying to adapt in engineering design, Critical need for University-Academia coloration etc.

Arindam Ghosh

Prof. Arindam Ghosh

Indian Institute of Science

Bio: Arindam Ghosh did his PhD at the Indian Institute of Science, Bangalore, following which he worked in Cambridge University, UK, as a post doctoral researcher. He returned to IISc, Bangalore in 2005, becoming full Professor in 2017. He has been a Visiting Research Fellow in Nanotechnology at the T J Watson Research Center of IBM. He has received numerous prizes, including in December 2020 the Infosys Prize for Physical Sciences for his development of atomically thin two-dimensional semiconductors to build a new generation of functional electronic, thermoelectric and optoelectronic devices.

Talk Title: Fundamentals of thermoelectric engines with twisted 2D bilayers of graphene

Abstract:  Thermoelectricity is an unconventional but extremely sensitive probe to the effects of electronic interactions in solids. Thermoelectric measurement often complements standard electrical transport and detects electronic correlations through departure from the well-established Mott semiclassical framework. Recent emergence of twisted bilayers of graphene provides a new versatile platform to explore not only several fundamental aspects of thermoelectricity at the atomic scale, but also design a new class of thermoelectric devices. I shall present how thermoelectricity can probe the inter-layer coupling in twisted bilayers, and exploit the understanding in realizing a unique class of heat engines.

Ranjan Singh

Prof. Ranjan Singh

NTU Singapore

Bio: Ranjan Singh is an Indian scientist and an Associate Professor at Nanyang Technological University (NTU) Singapore. He received B. Eng. in Telecommunications from Bangalore University (2001), M. Tech in Photonics from Cochin University (CUSAT), and a Ph. D. in Photonics from Oklahoma State University (2009). During 2009-2013, he was a postdoc at the Los Alamos National Laboratory. He founded TeraX Labs in 2013 at the Division of Physics, NTU Singapore. He is an elected fellow of OPTICA (OSA) for pioneering contributions in ultrafast terahertz photonics, active metamaterials, and sensors. His current research interests include terahertz electronic-photonic hybrid technologies for 6G communications, intelligent metasurfaces for beamforming, THz topological photonics, THz spintronics, quantum materials, and chalcogenide micro-nanophotonics. He has raised US$ 12M in competitive research grants, including a US $7M to develop on-chip terahertz topological photonics for 6G communication (TERACOMM). He has been listed as one of the top 1% of highly cited researchers by the web of science in 2020 and 2022.

Talk Title: Terahertz Silicon Topological Photonics for 6G communications

Abstract:  Global digitalization and the recent rise of artificial intelligence-based data-driven applications have directed their vectors towards terabits per second (Tbps) communication links. The fast-evolving 5G communication network cannot fulfill this demand due to several technological challenges, including bandwidth scarcity, which has stimulated innovative technologies with a vision of 6G communication. Terahertz (THz) technologies have been identified as a critical candidate for the emerging 6G communication with the potential to provide ubiquitous connectivity and remove the barrier between the physical, digital, and biological worlds. Nonetheless, the existing THz photonic on-chip communication devices suffer from backscattering, bending loss, limited data speed, and lack of active tunability. Here, I will describe a new class of on-chip THz photonic topological devices consisting of low-loss, broadband single channel 160 Gbit/s communication link and critically coupled high-Q (Q ~ 106) cavities built on Silicon Valley-Hall Photonic Crystal. Silicon topological photonics will pave the path for augmentation of CMOS-compatible hybrid electronic-photonic driven terahertz technologies, vital for accelerating the development of 6G communications that would empower societies with real-time terabits per second wireless connectivity for network sensing, holographic communication, cognitive internet of everything, and massive digital cloning of the physical and the biological world.

Kaushik Basu

Prof. Kaushik Basu

Indian Institute of Science

Bio: Kaushik Basu received the BE. Degree from the Bengal Engineering and Science University, Shibpore, India, in 2003, the M.S. degree in electrical engineering from the Indian Institute of Science, Bangalore, India, in 2005, and the PhD degree in electrical engineering from the University of Minnesota, Minneapolis, in 2012, respectively. He was a Design Engineer with Cold Watt India in 2006 and an Electronics and Control Engineer with Dynapower Corporation USA from 2013-to 15. He is an Associate Professor in the Department of Electrical Engineering at the Indian Institute of Science. He served as the Technical Program Committee Vice-Chair of IEEE ECCE 2019 and 2022. In 2019, he received the Prof. Priti Shankar Teaching Award from IISc. As a co-author, he received the Second Best Prize Paper Award from IEEE Transactions on Transportation Electrification in 2021. He is IEEE senior member and is the founding chair of both IEEE PELS and IES Bangalore Chapter. He is an Associate Editor of IEEE Transactions on Power Electronics and IEEE Transactions on Industrial Electronics. His research interests include most aspects of Power Electronic converter design from a few kW to a few MW for applications ranging from space, grid integration of renewables and storage to fast charging of electric vehicles.

Talk Title: Characterisation and Modelling of the Switching transitions of WBG Devices

Abstract:  Silicon Carbide MOSFETs (SiC MOSFETs) fall into the class of wide band gap (WBG) power devices. These devices are commercially available in the voltage range of 600-3300V and compete with the state-of-the-art Si-insulated gate bipolar junction transistors (IGBTs). Superior material properties of SiC MOSFET lead to smaller die sizes. This results in faster switching transients and lower switching loss. However, it excites device and circuit parasitic that may lead to prolonged oscillation, high device stress, spurious turn-on and EMI-related issues. So, the benefit of using SiC MOSFET as a power device comes with numerous design challenges resulting in slow commercial adaptation. It is predicted that the overall market share of WBG devices (SiC and GaN together) will be roughly 10% of the total market for power semiconductors by 2025. To overcome the design challenges and fully utilise the benefits of fast-switching SiC MOSFETs, a better understanding of switching dynamics is essential. However, the switching dynamics of SiC MOSFET are different compared to its Si counterpart due to the highly non-linear device characteristics and participation of circuit parasitic in the process. In this talk, we will discuss our recent work on developing an analytical model of the switching dynamics for hard and soft transitions of SiC MOSFET by simplifying the complex non-linear dynamics predicted by the behavioural model. The developed model, given the device-related parameters extracted from the data sheet, estimated or measured circuit parasitic, can predict lost switching energy, rate of change of device voltage etc., necessary for a successful power converter design through computation with sufficient accuracy.

Hussam amrouch

Prof. Hussam Amrouch

University of Stuttgart, Germany

Bio: Prof. Amrouch is the head of the Chair of Semiconductor Test and Reliability (STAR) within the University of Stuttgart, Germany. He received his Ph.D. degree with the highest distinction from KIT, Germany in 2015. He currently serves as Editor at the Nature Portfolio for the Nature Scientific Reports Journal. He has around 190 publications (including 76 journals) in multidisciplinary research areas across the computing stack, starting from semiconductor device physics to the system level.

Talk Title: HW/SW Codesign for Reliable Brain-inspired Computing on Unreliable Ferroelectric FET Technology

Abstract:  In this talk, I will focus on the emerging ferroelectric technology and its great potential in building efficient in-memory computing architectures. I will present the key challenges that the FeFET technology currently faces w.r.t scaling, design-time and runt-time variability, read/write disturbance, and high write voltage. Then, I will present unprecedented dual-port FeFET which is completely disturb free demonstrating its ability to offer scaling down the FE layer thickness down to merely 3nm while still reliably storing 8 states (i.e., 3-bit MLC-FeFET). Further, I will explain how abstracted reliability models can be developed from device physics to circuits towards realizing HW/SW codesign for robust in-memory computing that outstandingly synergizes with and brain-inspired Hyperdimensional computing.

Ankush Bag

Dr. Ankush Bag

Indian Institute of Technology Guwahati, India

Bio: Dr. Ankush Bag is presently working as an assistant professor at IIT Guwahati since December 2021 after completing 5.5 years at IIT Mandi. He completed his PhD from IIT Kharagpur in 2016 on GaN devices including epitaxial growth, fabrication and characterization of GaN HEMTs. Presently his research interests are ultra-wide bandgap semiconductors such as Ga2O3 for both high power as well as optoelectronics applications.

Talk Title: Device Engineering for Ga2O3 based High Performance Deep UV Detectors

Abstract:  Gallium Oxide is an emerging ultra-wide bandgap semiconductor for the detection of deep UV rays around 254 nm. Apart from the direct band gap of ~4.9 eV, there are a few more material advantages of Ga2O3 such as good stability, high absorption coefficient, easier synthesis, etc. Although there have been remarkable developments in this domain across the globe during the last few years, still there are ample scopes for further improvement of these detector performances considering responsivity, the tradeoff between responsivity and dark current, and speed. In this regard, we attempted to improve the performance of these detectors by engineering heterojunction, PN junction, plasmon, etc.

Soumya Dutta

Dr. Soumya Dutta

Indian Institute of Technology Madras, India

Bio: Soumya Dutta is an Associate Professor in the Department of Electrical Engineering, IIT Madras. Apart from publishing more than 50 journals, proceedings and 2 books, he is holding several Indian and International patents and a recipient of awards like Young Scientist Award by European Materials Research Society, Unlock Ideas award by LAM Research etc. His current research interests are in various electronic and optoelectronic devices such as thin film transistors, solar cells, photo-transistors etc. based on organic semiconductors and perovskite materials, AMOLED display, polymer-based SAW devices, and graphene based NEMS devices.

Talk Title: Solution-based Organic Thin Film Transistor Technology Towards Circuits: Challenges and Possible Solutions

Abstract:  Substantial progress in organic thin film transistor (OTFT) has emerged the possibilities of realizing analog circuit applications such as low frequency amplifier for sensors, backplane circuits for flexible display, image sensors etc. Going forward, a number of scientific and technological challenges need to be addressed. Scalable manufacturing of OTFTs on polymer dielectric is one of the foremost challenges to make the technology sustainable. While scaling down the size, contact effect becomes the predominating factor deteriorating the device and circuit performances. Our research group actively involves in the development of solution based all-organic thin film transistors adapting microelectronic technology especially photolithography techniques to realize miniaturized high resolution device structure. In this presentation, our recent results on the technological aspects of scalable production of OTFT and alleviation of contact effect especially in solution-processed technology will be demonstrated.

Amit Agarwal

Prof. Amit Agarwal

IIT Kanpur, India

Bio: Prof. Amit Agarwal is a theoretical condensed matter physicist, working at the physics department of IIT Kanpur since 2012.

His research interests include topological materials, non-linear transport and optical phenomena, plasmons, and nanoscale device modelling.

Talk Title: Ultra-low-power steep-slope transistors based on laterally confined monolayer MoSi2N4

Abstract:  Leakage current in transistors has become a critical limiting factor for realizing ultra-low-power transistors. The dominant part of the leakage current arises from the long tail of the thermally excited carriers of high energy. We solve this problem by using narrow bandwidth semiconductors which limits the thermionic leakage current by filtering out the high energy carriers. We demon- strate this by using laterally confined and passivated monolayer MoSi2N4 as a channel material in two-dimensional transistors. With this solution, the subthreshold slope can be reduced to remark- ably low values of up to ∼ 20 mV/decade, compared to the thermally limited value of 60 mv/decade in conventional transistors at room temperature. We show that the unique electronic properties of narrow bandwidth conduction and valance bands is also shared by several other materials in the same series. This opens up new avenues for effectively tackling the OFF state current leakage and power dissipation problem and realizing ultra-low-power transistors.

Arun Joseph

Mr. Arun Joseph

IBM, India

Bio: Arun is the senior engineering leader of the Hardware Electronic Design Automation Group at IBM India Systems Development Lab. His areas of interest are hardware debug, energy efficiency, and cloud-native EDA platforms. He received IBM Outstanding Technical Achievement Awards in 2015 and 2019. Arun was recognized as IBM Master Inventor in 2020. In 2018 Interesting Engineering (IE) featured one invention in “15 Of the Most Interesting Patents Acquired In the Past 5 Years” placing IBM at #10. Arun has 20+ publications across premier international conferences & journals (including DAC/ISLPED/ICCAD/JETC/IET). He enjoys interacting with students and academia, and was awarded SRC Outstanding Industry Liaison in 2022.

Talk Title: Design Automation for concurrent design in emerging technologies

Abstract:  With the drive to sustainable reliable IT, the onus for extracting the maximum performance from technology migrations lies in newer design paradigms, and methodologies. In this talk will highlight some emerging technology trends, and illustrate its implications to hardware design, specifically high performance chip design, which in terms necessitates innovation in Electronic Design Automation (EDA). I will delve more into challenges in characterization of timing, power, noise, and reliability. I will also highlight some Cloud & AI/ML techniques leveraged for efficient industry scale designs, before concluding with how these tie into a concurrent design philosophy of hardware design.

Akshay K Naik

Prof. Akshay Naik

Indian Institute of Science, Bangalore, India

Bio: Akshay Naik completed his B.Sc. Physics from University of Mumbai and M.Sc. Physics from IIT Bombay in 1997 and 1999 respectively. He completed his Ph.D. from University of Maryland, College Park in 2006. After a short stint as a post-doctoral associate at University of Maryland, he moved to Caltech. He worked there first as Postdoctoral Scholar from Nov 2006 to July 2008 and then as Research Scientist from August 2008 to Nov 2011. He is currently Associate Professor with Centre for Nano Science and Engineering at Indian Institute of Science Bangalore. His current research interests include nonlinear dynamics in ultrathin nanoresonators and physics and application of electro and opto mechanical systems.

Talk Title: Linear and nonlinear effects in 2D Suspended Structures

Abstract:  Vibrating membranes fabricated using 2D materials are extremely sensitive to various stimuli. In this talk, I’ll present our efforts towards using these thin structures as sensors. One of these is a strain sensor fabricating using graphene on a thin silicon diaphragm. These tiny structures vibrate at very high frequencies (10-100MHz) and are exquisitely sensitive to changes in the strain. However, nonlinearities in these devices also constraint their use as linear sensor. In the talk, I’ll demonstrate methods for controlling and manipulating these nonlinearities. I’ll show how our inability to produce perfect devices leads to nonlinear effects and our ability to control and cancel out nonlinearities leads to enhancement of signal to noise ratio. This regime of near cancellation of the two strongest nonlinearities is not only useful for applications but also to observe higher order nonlinearities and nonlinear damping.

Andrew Green

Dr. Andrew J. Green

Air Force Research Laboratory, United States

Bio: Device research team lead at AFRL. Work involves the development of GaN devices for novel RF solutions as well as Ga2O3 towards the commercialization of the first UWBG semiconductor for high voltage converter applications. He has been with AFRL for 9 years since completing his PhD in Chemistry at Ohio University in 2013.

Talk Title: Development of Ga2O3 devices and diodes towards converter applications at AFRL

Abstract:  Ga2O3 device development has seen rampant progress over the past decade due to the combination of the availability of high quality substrates, epitaxial doping capabilities and the material’s field strength. This talk will discuss process modules which has enabled high DC conduction loss and dynamic switching loss figures of merit. Key process modules include gate scaling, implantation optimization, self-aligned processes and dielectric optimization.

Usha Gogineni

Dr. Usha Gogineni

AMS OSRAM, India

Bio: Dr. Usha Gogineni is the Director for EDA (Electronic Design Automation) in ams-OSRAM, India. Her team develops novel solutions and methodologies for compact modelling, and analog and digital design enablement. Usha holds an MS degree from Auburn University and a PhD from Massachusetts Institute of Technology. Her professional interests include semiconductor technology development, reliability, compact modelling, and design enablement. Prior to joining AMS, Usha was with Maxim Integrated, Bangalore and IBM Microelectronics in the U.S.

Talk Title: Challenges in Compact Modeling for Integrated Optical Solutions

Abstract:  Optical sensors are omnipresent in electronic devices and equipment used in the consumer, automotive, industrial and medical fields. Integrating these sensors into CMOS technologies leads to a unique set of challenges to the compact modeling of the sensors, as well as the other semiconductor devices used in the read-out circuitry. This talk will focus on the modeling challenges pertaining to the optical solutions in the consumer space, including proximity sensors, ambient light sensors, time of flight sensors and CMOS image sensors.

Kiran kumar

Dr. M V A Kiran Kumar

Intel Fellow, Intel, India

Bio: Kiran is Intel Fellow and recognized as an industry-wide expert in Formal Verification and is responsible for defining and executing FV on IPs and SOCs from all Intel design organizations. Kiran technically mentors and leads the largest formal team in the industry by growing the talent from within and outside Intel. Kiran works with industry/academia to bring in cutting edge innovations in FV to Intel. . He co-authored a book on Formal verification and authored more than 100 papers, internal and external and received more than 15 best paper awards. His motto is to make formal verification mainstream in the design cycle and owes his success to his strong team of FV enthusiasts and experts.

Talk Title: Formal Verification: Ready for Rapid Growth

Abstract:  The increasing ubiquity and complexity of electronics in the semiconductor industry demands the accurate and accelerated verification of designs. Formal verification has emerged as a promising technique to surpass the shortcomings of the dynamic verification method and ensures complete coverage. Formal methods are applied at different stages of the IP cycle. We present a concise yet informative “Formal Verification Roadmap” which would be of interest to executives and management who are at different levels of embracing formal methods: right from a nascent stage of building a formal centric team all the way until harnessing the power of formal as a mainstream verification methodology.

Dr. Vamsi K. Paruchuri

ASM International N.V., Netherlands

Bio: Dr. Vamsi Paruchuri is currently Head of Corporate R&D at ASM International, a leading supplier of semiconductor wafer processing equipment. Before joining ASM in 2017, Dr. Paruchuri was at IBM for 14 years researching semiconductor materials and processes ranging from high-k/metal gate to interconnects. Dr. Vamsi Paruchuri holds a Ph.D. degree from University of Utah and is author or a coauthor of over 80 journal and conference publications and more than 100 granted patents.

Talk Title: Atomic Layer Deposition (ALD): An essential process for advanced semiconductor technologies

Abstract:  yet to share

aspro Ajay PandeyAssociate ProfessorSchool of Electrical Engineering & Robotics

Prof. Ajay Pandey

Queensland University of Technology, Brisbane, QLD, Australia

Bio: Associate Prof Ajay Pandey is a tenured academic at the School of Electrical Engineering and Robotics at the Queensland University of Technology, Brisbane, Australia. He specialises in intelligent electronic systems and advanced optoelectronics sensors with a focus on their translation for application areas including neuroengineering, wearable electronics, medical robotics, and bionics.

Talk Title: Advanced optoelectronic platform technologies for neuroengineering and robotics

Abstract:  Close loop and intelligent sensing systems with high specificity are vital to the progress of robotics and neuroscience. In neuroscience, we need neuro-engineering tools that can map ensemble of neurons in the brain with micron-resolution to understand the complexity associated with neuronal circuits, while on the other hand we need energy efficient and up-scalable technologies that can capture mechanical interactions between an object with the elegance of human skin for solving the physical manipulation challenge in robotics. In this talk, I will introduce prospects and examples of molecular optoelectronic systems that are suitably positioned to provide micro and macro level sensing. The suitability of this platform technology for optoegentics, proprioception and in form of robotic skin will be discussed.

Saibal Mukhopadhyay

Prof. Saibal Mukhopadhyay

Georgia Institute of Technology

Bio:  Saibal Mukhopadhyay received a Ph.D. degree in electrical and computer engineering from Purdue University, West Lafayette, IN. He is currently a Joseph M. Pettit Professor with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta. His research interests include design of energy-efficient, intelligent, and secure systems. Dr. Mukhopadhyay is a Fellow of IEEE.

Talk Title: On-chip Acceleration of Radio Frequency Machine Learning Models

Abstract:  The machine learning (ML) models have gained significant attention for radio frequency (RF) applications. However, incorporation of these models in a wideband RF system pipeline faces intriguing challenges to satisfy requirements of low processing latency and high processing throughput under the constraint of low processing power. This talk will discuss algorithm-hardware co-design methods for energy-efficient accelerations of RFML models using automatic modulation classification task as a case-study. First, we will discuss a quantization-aware accelerator design methodology to improve maximum throughput and power-efficiency of AMC model. Second, we will discuss hybrid processing pipeline that couples signal processing and machine learning to further improve ML models for AMC. Third, we will discuss potential of in-memory computing in RFML accelerations. The talk will conclude with discussions of future research directions in this field.

Shekar Mallikarjunaswamy

Dr. Shekar Mallikarjunaswamy

Alpha and Omega Semiconductor Ltd

Bio:  Dr. Shekar Mallikarjunaswamy is the VP of IC and TVS technology at Alpha and Omega Semiconductor, USA. Prior to this he has held various management and engineering positions at Micrel, Impala Linear and Siliconix. He has over 30 years of experience in Power IC technology, design and product development. He graduated from NCSU-USA (Ph.D) and IIT-Madras (B.Tech, M.Tech), holds over 100 US & International Patents, 2 IEEE best paper awards and numerous publications.

Talk Title: TVS Technology, Products and Applications

Abstract: Transient Voltage Suppressors (TVS) are primarily used on-board to protect sensitive I/O and power supply pins of Integrated Circuits (ICs) from being damaged by system level ESD (IEC61000-4-2 and IEC61000-4-5). Rapid growth in high-speed ports for USB and HDMI applications have increased the market demand for low capacitance protection products. Although, the system level ESD protection devices can be monolithically integrated on-chip, the die cost increases. In addition, it is difficult to exceed the performance of standalone TVS that utilize special cost-effective process technology that is not available in advanced CMOS nodes. This talk will present the state-of-the-art TVS technology, package and product characterization for USB, HDMI and Ethernet applications.

Milind Dighrasker

Dr. Milind Dighrasker

Infineon Technologies

Bio:  Milind comes has 18+ years of industry experience in designing power electronics systems. He holds Master’s degree in power electronics from IIT Kanpur and has got several patents in the power electronics domain to his credit. He has been involved in designed and architected products for UPS, Solar Inverter, DC-DC converter, On Board charger & wireless charger application. His interests are Bi-Directional DC-DC converters, Wireless charger and High-power density designs.

Talk Title: WBG Devices and it’s

Abstract: The adoption of WBG in industry is rapidly increasing for power electronics systems. The choice of power train stage, topology, switching frequency etc. for WBG adoption, have been always a crucial decision points for system designers. This talk highlights few emerging systems where WBG adoption can make a large impact on system performance, features & power density. In this talk, few select systems power train & possible topologies for each stage of the power train will be analyzed. The impact of using WBG for each stage/topology will be analyzed by design examples.

Branson belle

Dr. Branson Belle

SINTEF, Norway

Bio: Dr. Branson Belle is a Senior Scientist at SINTEF, Norway’s largest research institute. He is a graduate of The University of Manchester U.K. where he completed both his undergraduate and PhD degrees. His PhD focused on magnetism in nanopatterned ferromagnets, specifically domain formation and switching field distributions. He is also a previous member of the condensed matter research group at Manchester, working under Sir Prof Andre Geim and Sir Prof Konstya Novoselov, 2010 Nobel laureates for their work on graphene. He has also spent time in industry, co-founding 2-DTech Ltd, a 2D material and device spin out and working as Director, Research and Technology insourcing for Thinfilm Electronics ( Ensurge Micropower) ASA, a printed electronics company which developed printed temperature smart labels. His current research focuses on 2D material devices for sensing applications as well as multi physics Atomic Force Microscopy.

Talk Title: Transition Metal Dichalcogenides based Heterostructures for Ultra-sensitive Environmental Gas Sensors

Abstract: The isolation of graphene has heralded a new class of material research in 2D materials. Due to their high mobilities, tuneable bandgaps and surface to volume ratios, 2D materials have shown promising performance as gas sensors. Moreover, heterostructures can further enhance sensitivity and other device properties. Details of heterostructure gas sensor assembly and adhesion between 2D materials will be discussed. Additionally, the performance of these gas sensors and their sensing mechanism will be presented.

Saptadeep Pal

Dr. Saptadeep Pal

Auradine Inc., USA

Bio: Saptadeep Pal is the Founding Principal Engineer at Auradine, Inc., a startup focused on building sustainable, scalable and secure hardware solutions for next-generation web applications. He helps define ultra-low power circuits and architecture solutions for highly energy-efficient hardware products at Auradine. He received the B.Tech. degree in electrical engineering from IIT Patna, Patna, India, in 2015 and the M.S. and PhD degrees in Computer Engineering from the University of California at Los Angeles, CA, USA, in 2017 and 2021 respectively. His research at UCLA was focused on design and architecture of packageless and wafer-scale processor systems based on novel high-performance interconnect fabrics.

Talk Title: Waferscale Computing

Abstract: Fueled by the tremendous growth of new applications in the domain of big-data computing, deep learning, and scientific computing, the demand for increasing system performance is far outpacing the capability of conventional methods for performance scaling. Traditionally, performance and energy scaling has relied on transistor and silicon scaling. However, developing chips, often very large ones in the advanced technology nodes, is becoming very challenging and costly. Moreover, system performance is often limited by inter-die connections. Today, dies with different functionality are packaged and integrated using PCBs. Unlike silicon features, package and PCB features have barely scaled (about 4-5x) over the past few decades. This severely limits performance and efficiency of processor systems. Traditional scale-out system building, and integration methodologies are failing to deliver the performance today’s applications (such as artificial intelligence, big-data processing etc.) demand. As a consequence, future performance, power, and cost improvements cannot come from transistor technology alone. Then, how do we enable “System scaling”?

To target scale-out systems, we propose chiplet-based waferscale processors to dramatically reduce inter-die communication overheads. To that end, we developed the Si-IF technology where bare dies can be tightly integrated on a waferscale interconnect substrate to build scale-out processors up to a size of an entire wafer. However, building such a large consolidated waferscale system has its own challenges. For the first time, we explored the design space of waferscale power-delivery networks, cooling and trade-offs of yield and inter-GPM network topologies, etc. I will discuss some of these challenges and solutions that we developed to architect a large shared memory waferscale prototype system. Next, I will make a case for waferscale GPU and waferscale graph acceleration, where we leverage the massive bisection bandwidth and sub-1ns inter-die latencies to build high-performance computing systems. Our work shows that massive gains in excess of 5-10x can be achieved in terms of both performance gains as well as system energy using waferscale integration.

IEEE Social Media Imageshttps://ieee-ipc.org

Prof. Biswanath Chakraborty

Indian Institute of Technology Jammu

Bio: Dr. Biswanath Chakraborty is an Assistant Professor at the Department of Physics at IIT Jammu. He received a Ph.D. degree from the Department of Physics, Indian Institute of Science, Bangalore, followed by posy doctoral stints at IISc and City University of New York, USA.
He has authored several manuscripts in peer-reviewed journals, and his research focuses on exploring light-matter interaction in two-dimensional van der Waals materials.

Talk Title: Quantum emitters in 2D materials

Abstract: Developing quantum emitters in a deterministic way to address future quantum information technologies has propelled intense activities in the recent past. Various studies on a wide variety of materials have been conducted to find out ideal sources of a robust and high-purity single photon. Atomically thin van der Waals materials with unique properties have been explored for developing single photon emitters that can even be integrated with photonic platforms.
Here we discuss the generation and characterization of such quantum emitters operating at room temperature. We perform time correlation measurements to establish single-photon properties.

Shin-ichi NISHIZAWA

Prof. Shinichi Nishizawa

Kyushu University, Japan

Bio: S.Nishizawa received the B.Eng, M.Eng, and Dr.Eng. in chemical engineering from Waseda University, Japan, in 1989, 1991, 1994, respectively. Then, he joined Waseda University as a research associate. In 1996, he joined the Electrotechnical Laboratory, Japan (since 2001, the National Institute of Advanced Industrial Science and Technology). Since, 2017, He has been a Professor of Kyushu University. His research interests include semiconductor wafer technologies for power devices, power electronics components and systems.

Talk Title: Recent Progress of scaled Si-IGBT and related technologies

Abstract: For the future power devices, Si-IGBT is still under improvement. To achieve more high power densities, size reduction, etc., there are many researches related to Si wafer, device processes, device structures, etc. are ongoing. In this presentation, the scaled Si-IGBT as the future advanced Si-IGBT, and related wafer, processes technologies are explained.

Arunkumar Gopal

Dr. Arunkumar G

Vellore Institute of Technology (VIT), Vellore, Tamil nadu, India

Bio: Dr. G. Arunkumar (Member, IEEE) received the Ph.D. from Anna University, India, in 2017. He is presently an Associate Professor with SELECT, VIT-Vellore. His research interests include DC –DC/AC converters, boost inverters, grid-connected converters, EV battery charging, electric spring, and tuning of memory elements and controller parameters using soft-computing techniques for power converters, modeling of converters. He is a co-inventor of “Vehicle to Grid and Grid to Vehicle Wireless Charger”.

Talk Title: Silicon Device Based Power Electronic Converters – Applications and Research in Power Electronics

Abstract: Silicon devices have been in use for a long time for power applications. MOSFETS, IGBTs, SJ MOSFETS, GTOs and other devices have been used in power converters for applications such as Electric Vehicle (EV) battery charging, wireless charging, DC gird, renewable – fed converters, etc. The expertise of our team is in hardware implementation of these converter topologies. Various non-isolated and isolated converters have been tested and validated with for these applications and for simultaneous charging of multiple Li – ion batteries of different ratings, CLLC converter for charging of multiple batteries, patented wireless charging of 48 V battery from a 36 V source etc. A discussion of the implementation of these projects with practical tips for researchers will be a major taking point of the talk.

Ganesh Subbarayan

Prof. Ganesh Subbarayan

Purdue University, USA

Bio: Ganesh Subbarayan is a Professor of Mechanical Engineering at Purdue University and the Co-Director of the Purdue-Binghamton SRC Center for Heterogeneous Integration Research in Packaging (CHIRP). He is a recipient of the 2022 SRC Technical Excellence Award and the 2005 Excellence in Mechanics Award from the ASME EPP Division. He is a Fellow of ASME as well as IEEE, and he served as the Editor-in-Chief of IEEE Transactions on Advanced Packaging during 2002-2010.

Talk Title: Accelerated Modeling for Design Space Exploration of Heterogeneously Integrated Systems: Is Machine Learning Useful?

Abstract: Modeling for design space exploration of Heterogeneously Integrated (HI) systems is well understood as a multi-physics problem but is less commonly recognized as a multi-scale problem. In this talk we systematically explore (1) adaptive grid solution strategies for systematic trade-off between solution accuracy and computational speed, (2) decomposition of problem domain to enable compact models of sub-domains [3] and to enable a coordinated multi-level analysis, (3) machine learning models as compact models of decomposed domains, and (4) the computational cost of training and using machine learning models relative to physical models. We will conclude with potential strategies for the efficient design exploration of HI systems including Physics Informed Neural Networks (PINNs).

Prof. Ritesh Agarwal

University of Pennsylvania

Bio: Ritesh Agarwal is a Srinivasa Ramanujan Distinguished Scholar and Professor in the Department of Materials Science and Engineering at the University of Pennsylvania. His group researches the role of quantum geometry and topology in electronic and optical systems and to engineer light-matter interactions to enable-chip chiral optoelectronics. Ritesh is the recipient of the NSF CAREER, NIH Director’s New Innovator and the SPIE Nanoengineering Pioneer awards. He is a Fellow of the Optical Society of America.

Talk Title: Utilizing Quantum Geometry and Topology for Enabling Integrated Chiral Photonics

Abstract: Classical and quantum computing devices need to ferry vast amounts of data and optical interconnects provide a promising approach allowing faster speeds and larger bandwidths. Critical interconnect components are light sources, waveguides and detectors. Currently, the information is encoded in intensity and frequency but other degrees of freedom (DOFs) such as photon-spin and spatial orbital angular momentum modes (OAM) should be utilized to enhance the capacity of optical links. Therefore, new materials and devices that can produce, transmit and detect light with complex polarization and spatial modes are needed. We will discuss recent developments towards the development of on-chip lasers, waveguides and photodetectors that are sensitive to photon spin and OAM modes that can enable the development of integrated chiral photonic systems.

Naga Phani B

Prof. Naga Phani B Aetukuri

Indian Institute of Science Bangalore, India

Bio: Naga Phani Aetukuri is an Assistant Professor in the Solid State and Structural Chemistry Unit at the Indian Institute of Science, Bengaluru. He received his doctoral degree from Stanford University in 2013 and was a post-doctoral researcher at IBM Almaden Research Center. His group’s research is in the areas of electrochemical energy storage materials and devices and thin film based electrochemical devices including organic electrochemical transistors.

Talk Title: Lithium Voids Precede Dendrite Growth in Solid State Lithium Metal Batteries

Abstract: Solid-state lithium metal batteries (SSLMBs) that utilize metallic lithium as an anode offer high energy density and potentially long cycle and calendar life. However, stable plating and stripping of lithium in cells employing inorganic solid electrolytes, especially at current densities >0.2 mA/cm2, has been a challenge. In this talk, we will discuss the origins of dendrite growth in SSLMBs employing inorganic solid-state electrolytes. We show that there is a strong correlation between the onset of dendrite growth and the observation of lithium voids at the interface with the solid electrolyte. We discuss the properties of interlayers and propose descriptors for identifying interlayers that could further increase the current densities for cycling lithium without the undue necessity for high stack pressure.

Ron Sinton

Dr. Ron Sinton

Sinton Instruments, USA

Bio: Ron Sinton did his PhD work at Stanford University, developing 28%-efficient silicon concentrator cells and 23% efficient backside-contact one-sun cells. He was a founding member of SunPower Corporation in 1988 and Sinton Instruments in 1992. The characterization methodologies that he developed, such as implied IV and Suns-Voc curves that combine measurements with device-physics analysis, have achieved widespread use within R&D and manufacturing. He was awarded the IEEE PVSC Cherry award in 2014.

Talk Title: Advanced Characterization of Silicon Solar Cells and Materials

Abstract: The electronic quality of silicon material and wafer bulk and surface recombination can be tracked through the entire value chain during ingot to solar cell to module manufacture. This talk will describe the use of excess-carrier-lifetime measurements throughout the process. In addition to applying this technique for process optimization and control, the use of lifetime measurements to study the various degradation mechanisms under light and temperature stress for high-efficiency solar cells will be described. This will include eddy-current lifetime-measurement techniques as well as the interpretation of current-voltage and additional data at the cell, module, and array tests.

Meena mishra

Dr. Meena Mishra

DRDO,INDIA

Bio: I have been serving in DRDO since 1989. My core area of research is RF Circuit Design and Characterisation along with high frequency and high power device design. I have Developed the small signal, nonlinear and noise models for high frequency devices like MESFET,HEMTand PHEMT. Developed design kits for the in-house developed devices. Designed and fabricated MIC low noise amplifiers with less than 1dB Noise Figure and high power amplifiers with power output of 1.5 kiloWatt.Presently working on design of GaN HEMT based MMIC and development of high power GaN MMIC technology.Main area of interest is in RF Characterisation ,modeling of low noise and high power
HEMTs and MMIC design.Presently working as Technology director on various state of the art projects. Successfully designed and developed GaN based wideband and narrowband Fr
MMIC power amplifiers, low noise amplifiers ,SPDT switch and multifunction circuits in S,C,X and Ku bands.

Talk Title: Indigenous GaN MMIC Technology

Abstract: Future trends for next generation strategic systems require multifunctionality and modularity like combining radar, communications, and electronic warfare in one system. This higher level of functional integration improves system performance through heightened awareness, improved responsiveness, and mission execution. The use of gallium nitride (GaN) MMIC as key component enables higher performance of systems meeting the requirements in small size with high power and hence GaN MMIC are emerging as an alternative or replacement for laterally diffused MOSFET (LDMOS) components. In most of next generation systems GaN MMIC technology is being considered because of high power density, high efficiency, wide bandwidth, and exceptionally long life. GaN on SiC has superior properties like higher breakdown voltage; higher saturated electron drift velocity and higher thermal conductivity. Hence GaN HEMTs also offer greater power density and wider bandwidths compared to Si; GaAs; and GaN on Si transistors. As shorter gate length GaAs and GaN transistors become available, coupled with improved circuit design techniques, new devices are becoming available that can perform comfortably to millimeter wave frequencies, opening new applications that were hard to contemplate a decade ago. This paper will briefly describe the indigenous GaN semiconductor technology that is enabling these developments to achieve optimum performance of devices, circuits and subsystems based on this technology.

Peter Jepsen

Prof. Peter Uhd Jepsen

Department of Electrical and Photonics Engineering, Technical UNiversity of Denmark

Bio: Peter Uhd Jepsen has been active in the field of THz science and technology since 1993. His focus areas include fundamental and application aspects of generation, propagation, and detection of ultrashort pulses of coherent THz radiation, and he holds strong expertise within ultrafast laser optics, light-matter interactions, optical spectroscopy, and photonics engineering. He is Fellow of Optica (former Optical Society of America) and has published 145 peer-reviewed articles with >9600 citations and an H-index of 47.

Talk Title:  THz-driven strong-field lightwave electronics and nanoscale THz imaging

Abstract: Terahertz (THz) spectroscopy has been used for decades as a driver for the development of novel applications in sensing, nondestructive testing, and quality control. In the recent few years there has been an increased interest in using strong THz field for technologies that are close to fundamental research, but still is close to commercial use. I will discuss our recent development of the world’s first THz-sensitive photomultiplier, THz-based imaging techniques for large-scale mapping of thin-film conductivity with focus on graphene in the semiconductor industry, and finally show the route towards mapping of thin-film conductivity with a resolution of 20 nanometers, using THz waves.

Vinod Menon

Prof. Vinod Menon

City College & Graduate Center CUNY

Bio: Vinod Menon is a Professor of Physics at the City College of New York and doctoral faculty at the Graduate Center of the City University of New York (CUNY). He is a fellow of the Optical Society of America and an IEEE Distinguished Lecturer in Photonics (2018-2020). Prior to joining CUNY, he was at Princeton University (2001-2004) where he was the Lucent Bell Labs Post-Doctoral Fellow in Photonics.

Talk Title: Polariton lasers in organic molecular materials

Abstract: Exciton-polaritons, half-light half-matter quasiparticles that form in optical cavities have become a highly attractive candidate to realize Bose Einstein like condensates in the solid state that emit coherent radiation. Also called polariton lasers, these systems show lower threshold than the more conventional photon lasers because they do not need population inversion. Organic molecules have emerged as an appealing system to realize polariton lasers owing to their ability to operate at room temperature. Following a brief introduction to polariton lasers, I will present our recent work on realizing a universal platform for achieving polariton lasing using commercially available dyes using a small molecule ionic isolation lattice (SMILES) host. Possibility to realize lattices of polariton lasers and their potential as analog Hamiltonian simulators will also be discussed.

Urbasi Sinha

Prof. Urbasi SInha

Raman Research Institute

Bio: Professor at the Raman Research Institute in Bangalore, India. Heading the Quantum Information and Computing (QuIC) laboratory at RRI, which specializes in experiments on photonic quantum information processing including quantum computing and quantum communication, primarily using single and entangled photons. Associate faculty member at IQC Canada, and CQIQC Canada. Completed both PhD and MSc in Physics at Cambridge University, UK. Was a post-doctoral research associate in the Cavendish labs, Cambridge as well as at IQC Canada.

Talk Title: How “quantum” is a quantum computer?

Abstract: We present two complementary viewpoints for combining quantum computers and the foundations of quantum mechanics. On the one hand, ideal devices can be used as test beds for experimental tests of the foundations of quantum mechanics: We provide algorithms for the Peres test for complex numbers in quantum superpositions and the Sorkin test of Born’s rule. On the other hand, noisy intermediate-scale quantum devices can be benchmarked using these same tests. These are deep quantum benchmarks based on the foundations of quantum theory itself. We present test data from Rigetti hardware and the IBM qiskit simulation platform.

Shweta Agarwala

Prof. Shweta Agarwala

Aarhus University

Bio: Shweta is an Associate professor at ECE, Aarhus University, Denmark and heads ‘Printed Electronics Technology’ laboratory. Her research vision is to build sustainable electronics through soft and biodegradable electronic materials. Her research group is working on building biodegradable material library with novel electronic functionalities and using 3D printing for flexible and bio-electronic devices with applications in healthcare, wearables, smart textiles and soft robotics. She obtained her Master’s at the prestigious Nanyang Technological University (Singapore) and later defended PhD at National University of Singapore (Singapore). She was a postdoc at the Energy Research Institute in Singapore, and later went to Singapore Centre for 3D Printing to pursue research in printed electronics before travelling to Denmark. Shweta is author of more than 50 peer-reviewed papers published in internationally renowned journals, conferences and books. She serves as the chair of IEEE Women in engineering Denmark section, and is an advocate of engaging more females in STEM.

Talk Title: Sustainable Electronic Materials and Devices

Abstract: Sustainability and health are two of the global challenges recognized by UN. Electronics is the pillar that supports the innovation in these sectors. However, current electronic components are non-biodegradable and release toxins in environment, while the implanted electronics is not compatible with soft human tissues. The aim of my research is to overcome these challenges through i) development of novel electronic material library, and ii) next-generation devices with new form factors. Through green chemistry we have developed novel biodegradable, biocompatible and bioresorbable electronic materials. Printed electronics is the new emerging fabrication technique that allows electronic components, circuits and devices to be put on a desired surface using nanoparticle inks. The synthesized materials are converted into printable inks to fabricate soft and flexible devices. I will showcase some of the case studies on the application of the materials and flexible devices.

Kranthi nagothu

Dr. Kranthi Nagothu

Texas Instruments, India

Bio:  Kranthi Nagothu obtained his PhD from Indian Institute of Science Bangalore and joined Texas Instruments, Bangalore in October-2020. His work in ESD Development Team, focuses on understanding the physics of different high voltage and low voltage analog ESD components. He worked on both component level and system level ESD problems before and after joining TI. He presented his work at major international conferences like IRPS, ISPSD, ESD Symposium. He also authored & co-authored several papers in Transaction on Electron Device journal.

Talk Title: On-chip System level IEC ESD protection issues in Automotive ICs

Abstract:  In this talk, unique failure mechanisms in high voltage Silicon Controlled Rectifiers (SCR) under IEC stress are discussed. In one case, the presence of a common mode choke in the stress path was found to change the current waveform shape that the electrostatic discharge (ESD) protection device experiences on-chip. Minor variations in the stress current waveform shape for specific IEC stress levels are found to cause an unexpected window failure in DeNMOS based SCR. In second, Air-Discharge IEC failure in Bi-Directional SCRs that are sensitive to IEC measurement conditions via the pulse rise time are investigated. 3D-TCAD simulations are used to develop the physical Insights of the failure and propose the device level engineering solutions to mitigate the IEC failures.

Anbarasu M

Prof. Anbarasu Manivannan

Indian Institute of Technology Madras, India

Bio: Prof. Anbarasu Manivannan is a Professor in the Department of Electrical Engineering, jointly with the Department of Physics as an Interdisciplinary Faculty member in the area of Phase Change Memory Technology at IIT Madras. His research group focuses on development of phase change memory, 3D-XPoint Memory, multi-bit data storage technology and also phase change synaptic devices for neuromorphic computing. He serves as a member of the European Phase Change and Ovonic Symposium (E\PCOS) since 2020.

Talk Title: Phase Change Memory Technology for High Speed Computing

Abstract: In the realm of next generation computing, chalcogenide based Phase Change Memory (PCM) offers promising features for a ‘universal memory’ owing to all-round characteristics including high-speed and non-volatility. However, realizing an ultrafast switching is still a key challenge for faster programming. This talk will present exhaustive experimental results on electrical switching of Ge-Sb-Te, Ag, In-doped Sb2Te and In-Sb-Te based PCM devices including ultrafast electrical switching dynamics, voltage-dependent transient characteristics in picosecond timescale using a custom-built advanced programmable electrical test setup. Furthermore, a trajectory map for defining the ultimate speed of PCM devices will be discussed on the basis of field-dependent transient dynamics in picosecond timescale for enabling the ultimate speed of PCM devices would pave a way towards realizing ‘universal memory’ for future computing.

Raveesh Magod

Dr. Raveesh Magod

Texas Instruments, USA

Bio: Received the M.S. and Ph.D. degree in EE from Arizona State University in 2014 and 2018 respectively. Since 2017, he is with Kilby Labs, Texas Instruments, USA, where he has been involved in R&D of wide range of power management products. He was the co-recipient of A.K. Chowdhary Best Paper award at the International conference on VLSI Design, 2021 and has five granted/pending U.S. patents. He also serves as a TPC member for the CICC.

Talk Title: Powering a sustainable future – Two important vectors enabling next-generation of energy efficient power management ICs

Abstract: Power management has been a key enabler for a variety of ever increasing modern day electronic applications like smartphones, data center servers, electric vehicles and smart grids to name a few. However, in order to achieve climate neutrality targets and also cater to surging energy consumption by such applications across the globe, it is imperative that such solutions need to be highly efficient. This talk focuses on wide-bandgap (GaN and SiC) based converters and ultra-low quiescent power converters, which are identified as two key directions for next-generation of sustainable power management ICs that achieve higher energy efficiency. Insights into latest industry products, ongoing research and future trendlines are discussed in detail.

Ayodhya Tiwari

Prof. Ayodhya Nath Tiwari

Empa-Swiss Federal Laboratories for Materials Science and Technology

Bio: Ayodhya Nath Tiwari is the head of Laboratory for Thin Films and Photovoltaics, Empa-Swiss Federal Laboratories for Materials Science and Technology, adjunct professor at ETH Zurich, and founder chairman of Flisom company. His field of research covers thin film solar cells for terrestrial and space applications, sensors/detectors, printed electronics and solid-state batteries. He is experienced in transfer of lab’s innovative research excellence to industrial manufacturing, application of thin film coating technologies, development of equipment and processes for various applications.

Talk Title: Thin film photovoltaic technologies: new trends, progress, opportunities and industrial challenges

Abstract: Thin film solar cells based on Cu(In,Ga)Se2 (called CIGS) and organic-inorganic hybrid Perovskite semiconductors have shown remarkably high photovoltaic conversion efficiencies on glass and flexible substrates in “monofacial”, “bifacial”, and “tandem” configurations. The trends of progress suggests efficiencies beyond 30% are within reach quite soon. Thin film photovoltaic (PV) technologies show great potential for low cost manufacturing and some specific features of solar modules are especially attractive for terrestrial and space applications. These technologies, different from Si wafer based technologies, offer new opportunities to industries but also pose various challenges. The talk will present status of technologies, emerging trends, and discuss the challenges and opportunities for industries.

Udayan Ganguly

Prof. Udayan Ganguly

IIT Bombay

Bio: Udayan Ganguly received the B.Tech. degree in Metallurgical Engineering from the IIT Madras, in 2000 and the Ph.D. degrees in Materials Science and Engineering at Cornell University, Ithaca, NY in 2006 respectively. In 2006, Udayan joined Applied Materials as the technical lead for Flash Memory Applications Development. His research interests are in semiconductor device physics and processing technologies for advanced memory, computing, and neuromorphic systems. He is an editor at IEEE Electron Devices Letters.

Talk Title: Manganite based RRAM for Stochasticity Control for Boltzmann Machine

Abstract: Non-filamentary manganite-based RRAM provides richness in behavior & controls due to the interplay of ionic, thermal, and electron conduction. We have shown that set & reset processes are enabled by positive vs. negative feedback leading to polarity-controlled stochastic vs. deterministic switching. The stochastic set enables a probabilistic switching in a neuron for a Boltzmann Machine. The deterministic reset enables excellent HRS control which enables weight update. Further, it enables highly controlled initialization of the HRS state that produces a very controlled stochastic switching distribution that remains drift free over time. Such stationary distributions enabled by deterministic/stochastic device physics produces improved performance in NP-Hard graphical optimization problems like maximum cut (Max-cut).

Merlyne M De Souza

Prof. Merlyne De Souza

The University of Sheffield

Bio: Merlyne De Souza received her PhD from the University of Cambridge in 1994. She was appointed Professor of Electronics and Materials at De Montfort University in 2003 and Professor of Microelectronics at the University of Sheffield in 2007. She has been a technical committee member of the IEDM (2012-2017) and IRPS (2003-2013). She has co-authored over 200 articles to date and is a distinguished lecturer and VP of membership of the IEEE Electron Device Society.

Talk Title: Revisiting doping mechanisms in a mixed electronic-ionic conductor PEDOT:PSS

Abstract: The mechanism of doping and de-doping in conjugated polymers such as PEDOT:PSS has been widely discussed on account of their application in bioelectronics from electrochemical batteries/supercapacitors to neural electrodes and transducers. In a conventional theory, there are three expected mechanisms of doping (i) Capacitive, leading to box shaped CV characteristics, whereby electrical double layers are formed at the surface of the polymer and the counter-electrode. This type of a film shows a capacitance independent of thickness. (ii) Faradaic, in which under positive bias, holes move towards the counter-electrode and react with species in the electrolyte leading to redox peaks in the cyclic voltammetry and (iii) Volumetric electrochemical doping, which is a combination of the above two, caused largely by cation injection into the bulk of the film, leading to electronic-ionic coupling of the holes and cations [1-3].
We demonstrate that the doping mechanism of K+ in PEDOT:PSS is more complex than these simple scenarios. Our films are able to retain more ions in a Faradaic reaction than via purely capacitive doping, pointing to coupling between the sulfonate anion and cation.
References:-
1.Exploiting mixed conducting polymers in organic and bioelectronic devices, Scott Keene et al Phys. Chem. Chem. Phys., 2022, 24, 19144
2. Understanding Volumetric Capacitance in Conducting Polymers, Christopher M Procter et al, Journal of Polymer Science, Part B: Polymer Physics 2016, 54, 1433-1436.
3. Berggren, M., Malliaras, G. G., (2019), How conducting polymer electrodes operate, Science, 364(6437), 233-234. https://doi.org/10.1126/science.aaw9295

Shubhakar Kalya

Dr. Shubhakar Kalya

Singapore University of Technology and Design (SUTD), Singapore

Bio: Shubhakar Kalya obtained his Master’s degree in Microelectronics from IISc, Bangalore, India (2007) and PhD degree from NTU, Singapore (2012/13). His research work focusses on nanoscale characterization of dielectrics for reliability and failure analysis. He has also worked as a researcher at A*STAR-IMRE, Singapore during 2009-2011. He was a Visiting Scientist at MIT, USA in EECS Department during Jan-June 2017. Currently, he is working as a Lecturer at Singapore University of Technology (SUTD), Singapore.

Talk Title: 2D Dielectric Materials for Emerging Nanoelectronic Devices

Abstract: Two dimensional (2D) dielectric materials are amongst the key drivers enabling the realization of next generation nanoelectronic devices in the future [1]. Hexagonal boron nitride (h-BN), 2D mica and Fluorinated graphene have recently attracted a lot of attention as 2D dielectric materials [2,3]. In particular, h-BN emerges as one of the promising dielectric materials for graphene and other 2D layered semiconductor based nanoelectronic devices. The h-BN exhibits perfect match for graphene as they share many similarities. Mica dielectric material used as a substrate for various heterogeneous 2D material structures due to its excellent thermal stability, surface flatness, light transmittance and chemical resistance. Fluorinated graphene is another 2D dielectric material which demonstrates excellent dielectric properties with fast and scalable processing. Importantly, there is limited insight and conclusive evidence on the physics of degradation, reliability and breakdown (BD) in these 2D dielectric materials. Here, we highlight important findings on the mechanism of degradation and BD in h-BN and Mica dielectrics from the device level to localized nanometer scale regions of 2D dielectrics. Nanoscale analysis tools (Conductive atomic force microscopy (CAFM) and transmission electron microscopy (TEM)) are used to assess the nanoscale performance of the 2D dielectrics; local degradation due to dielectric wear-out and subsequent breakdown.

Luis Jauregui

Prof. Luis A Jauregui

University of California, Irvine, USA

Bio: Luis did his undergraduate studies at UNI-Peru and worked as an undergraduate researcher at Texas A&M. In 2008, Luis started his Ph.D. at Purdue University, working in the electron and phonon transport of graphene and topological nanostructures. For his graduate studies, he obtained the Intel Ph.D. Fellowship and the Purdue Research Foundation Fellowship. After his Ph.D., Luis became a Postdoctoral fellow at Harvard and worked under the direction of Philip Kim, in collaboration with Hongkun Park, Misha Lukin, and Federico Capasso. Luis’ postdoc work was centered on studying the optical properties of van der Waals heterostructures. Since 2019, Luis is an assistant professor at the Physics Department at UCI and the director of the Irvine Quantum Material Center.

Talk Title: Strain-driven quantum devices

Abstract: Topological order and materials have been at the center of attention in condensed matter physics and engineering. Topological materials, a new quantum state of matter, are a family of quantum materials with boundary states whose physical properties are robust against disorder. Therefore, there have been few examples for a topological phase transition realized experimentally, even fewer cases for an in-situ tuning of the topological phase. For the first part of my talk, I will discuss our results
and methods to apply uniaxial strain in topological van der Waals quantum materials and how it influences its electrical properties. Our results point towards a topological phase transition of the system tuned by in-situ uniaxial strain. For the second part of my talk, I will discuss our approach to creating dynamic strain in van der Waals quantum materials and how to control the electron and excitons dynamics in such systems. Our results could pave the way for engineering novel quantum devices as well as a step towards a solid-state quantum simulator platform.

Zakaria Al Balushi

Prof. Zakaria Al Balushi

University of California, Berkeley

Bio: Zakaria Al Balushi is an assistant professor in the department of Materials Science and Engineering at UC Berkeley and a faculty scientist at the Lawrence Berkeley National Laboratory. Zakaria received his B.S., M.S. in Engineering Science and his Ph.D. in Materials Science and Engineering all from The Pennsylvania State University. Prior to his appointment at the University of California, Berkeley, he was a Resnick Prize Postdoctoral Fellows in Applied Physics and Materials Science at Caltech.

Talk Title: Spatially Controlled Growth of 2D Materials

Abstract: The surface potential of graphene can be modulated with strain and doping by engineering the underlaying sub-surface in which the graphene resides on. Here we discuss a detailed investigation to correlate the influence of the underlying sub-surface on modulating the surface potential of graphene on a diamond like carbon (DLC) substrate through a heterointerface containing trapped gallium in uniquely designed spatial structures. Through our heterointerface engineering approach of the graphene surface potential landscape, we show selective area growth of 2D materials on the graphene surface . This study will provide a deep understanding on the influence of graphene surface potential on the nucleation and surface diffusion process for the growth of chalcogenide 2D semiconductors.

Anand Bulusu

Prof. Anand Bulusu

Indian Institute of Technology Roorkee, Roorkee, India

Bio:  Anand Bulusu received the Ph.D. degree from IIT Bombay, Mumbai, India, in 2006. He worked as a Senior Research Engineer from 2007-08 in Silicon Technology Solutions groups of Freescale Semiconductor (present NXP Semiconductor). Since December 2008, he has been working as a faculty member in the Electronics and Communication Engineering Department of IIT Roorkee, Roorkee, India, where he is currently a professor. His current research interests include circuit performance models and design, device-circuit interaction, and digital/analog/mixed-signal circuit design.

Talk Title: Towards reliable circuits using NC/FEFETs

Abstract: In this talk, we mainly describe our work in understanding the physics of multiple domains, dielectric (DE) phase in FE layer, interface traps in NC/FeFET devices and their impact on circuit reliability. We also discuss the impact of polarization asymmetry in the FE layer due to drain-source voltage in NC/FeFETs. We discuss that the presence of DE phase causes non-uniformity in the polarization and potential contour inside the FE-layer in the gate-dielectric stack. The randomly varying fraction of DE phase, therefore, introduces a higher reliability concern for NC-FETs. In FeFETs, we observe and explain that there exists a certain DE percentage threshold below which the increase of the DE phase does not significantly impact the device memory window. We observe that another reliability issue in NCFETs is caused by the traps at the interfaces of silicon, silicon-di-oxide and hafnium oxide or bulk hafnium oxide traps, which change the FE polarization.

Muthukumaran Packirisamy

Prof. Muthukumaran Packirisamy

Concordia University, Montreal, Canada

Bio:  Packirisamy, Professor and Concordia research chair with Concordia University Canada, recipient I.W. Smith Award, University Distinguished Research Fellow, Petro Canada Young Innovator Award and ENCS Young Research Achievement Award. He is a member of Royal Society of Canada College and Fellows of National Academy of Inventors (USA), Indian National Academy of Engineering, Canadian Academy of Engineering, Engineering Institute of Canada, American Society of Mechanical Engineers, Institution of Engineers India, and Canadian Society for Mechanical Engineering.

Talk Title: MICRO-NANO INTEGRATED SYSTEMS FOR LIFE SCIENCE APPLICATIONS

Abstract:  In this presentation, we will talk about the in-situ synthesis of Au-PDMS and Ag-PDMS nanocomposites both at the macroscale and inside the channel of a microfluidic chip. The nanocomposite has been successfully used for sensing of antibody-antigen interactions, allowing the detection of various important proteins. Nanocomposites of metals integrated into other polymers such as PMMA, PVA, and PS have been synthesized as well by using UV, microwave and thermal reduction methods. The effect of the particle`s shape on the properties of nanocomposites and their sensing abilities has also been studied by synthesizing nanostar particles and integrating them into microchannels. Because of the biocompatibility and non-toxicity of gold and silver nanoparticles, their nanocomposites can be used for plasmonic detection of biological entities in cancer research.

Julien Ryckaert

Dr. Julien Ryckaert

imec, Belgium

Bio:  Julien Ryckaert received the M.Sc. degree in electrical engineering from the University of Brussels (ULB), Belgium, in 2000 and the PhD degree from the Vrije Universiteit Brussel (VUB) in 2007. He joined imec as a mixed-signal designer in 2000 specializing in RF transceivers, ultra-low power circuit techniques and analog-to-digital converters. In 2010, he joined the process technology division in charge of design enablement for 3DIC technology. Since 2013, he is in charge of imec’s design- technology co-optimization (DTCO) platform for advanced CMOS technology nodes. In 2018, he became program director focusing on scaling beyond the 3nm technology node as well as the 3D scaling extensions of CMOS. Today, he is vice president logic in charge of compute scaling.

Talk Title: CMOS scaling: From Design into System Technology Co-Optimization

Abstract:  Scaling is driven by the perspective of more function per unit cost. This paradigm has essentially been fueled with increasing transistor density by building ever more compact devices and finer interconnect capabilities. We are approaching records in feature sizes that starts questioning its viability moving forward. The entire Mendeleev table has been screened and manufacturing machines reach extreme levels in precision. However, an SoC is not composed of a monolithic set of functions, from compute blocks to memorization very different functions are expected from CMOS devices, not to mention the whole infrastructure that wraps the system (power and clock distribution, short signal nets and long signal nets, IOs and PLLs,…). The SoC is a vastly heterogeneous system. In order to keep scaling system performance, technology will not need to embrace that heterogeneity and find ways to leverage unique technology capabilities that improve system performance. This can only go hand in hand with a revision of system design practices and introducing novel architectures. CMOS Scaling is entering the era of System-Technology Co-Optimization. We will be talking about concepts leaning in that direction, such as backside processing and bonding technologies for smart partitioning, and extrapolate to the broader vision of the CMOS heterogeneous platform: CMOS 2.0.

Dipak Kumar Goswami

Prof. Dipak K. Goswami

Indian Institute of Technology Kharagpur

Bio:  Prof. Dipak K. Goswami is a professor in Physics at the Indian Institute of Technology Kharagpur He completed his Ph.D. degree from the Institute of Physics, Bhubaneswar, in 2004. Afterward, he worked at Northwestern University (NU), Advanced Photon Source (APS), USA, and Max Planck Institute for Metals Research, Stuttgart, Germany. His areas of interest are the growth of thin films, nanostructures, and the fabrication of various flexible organic electronic devices.

Talk Title: Flexible organic electronic devices in healthcare for remote patient monitoring

Abstract:  With the devastating COVID-19 pandemic spreading during the last two years, the need for smart-healthcare technology to take off the pressures of health professionals and provide the patient with much comfortable yet remote monitoring medical devices becomes paramount. Aligning the flexibility of organic electronic device-based sensors has been found to provide opportunities to develop wearable medical technology, including various diagnostic interventions to replace the existing gold standards with portable, affordable, and wearable medical devices with remote monitoring capabilities. In this talk, I will take on the development of a diagnostic intervention of pulmonary disfunction-related diseases, such as chronic obstructive pulmonary diseases (COPD) and sleep apnea, using a flexible organic field-effect transistors-based sensor system.

Jim John

Dr. Jim Joseph John

R&D center, Dubai Electricity and Water Authority (DEWA), UAE

Bio:  Jim Joseph John completed his Ph.D degree from IIT Bombay, India. He then worked at Huawei Technologies as researcher, and now works as a Sr. Scientist at Dubai Electricity and Water Authority (DEWA) R&D Center. His main research interests is reliability of PV modules for desert climates. He has authored 50+ conference proceedings and scientific journal papers, and 4 inventions. He has conducted several research projects with Stanford, Purdue University, Fraunhofer, CSEM, and ISC Konstanz.

Talk Title: Desert Photovoltaics – Performance and reliability issues of PV modules in hot climatic conditions

Abstract:  The photovoltaic industry has reached a major milestone of installed global capacity of 1TW. The desert regions are ideal locations for installing large power plants. However, the expectations of PV system operating for 20-30 years or more can be challenging due to the harsher climatic conditions. Therefore, improving the risk associated with weather-induced degradation of PV modules will reduce uncertainity in lifetime energy production, which in turn reduces financial risk and improves financing opportunities for projects located in these regions. In this talk, I will be sharing the degradation issues of different PV module types located in the 5GW MBR Solar park. The climate severity will be discussed, followed by its impact on the PV module BOM will be shown. Requirement for climate specific qualification standards and module design will be explored.

Tapas Dutta

Dr. Tapas Dutta

University of Glasgow, UK

Bio:  Tapas Dutta received the Ph.D. degree in nanoelectronics and nanotechnology from the Grenoble INP, France. Afterwards, he joined IIT Kanpur, India as a postdoctoral researcher. Since September 2017, he has been with the Device Modeling Group at the University of Glasgow, where he has been a co-developer of NESS (Nano Electronic Simulation Software). He was also with Semiwise Ltd., Glasgow during 2017-2021 where he worked on the development and commercialization of several new technologies.

Talk Title: Nano-Electronic Simulation Software (NESS): An Overview

Abstract:  In this talk, I’ll provide an overview of the new device simulator NESS (Nano-Electronic Simulation Software) developed by the University of Glasgow’s Device Modelling Group. It is a fast and modular TCAD tool with flexible architecture and has been implemented in C++. It has its own structure and mesh generation capabilities, and contains different modules including classical, semi-classical, and quantum transport solvers, mobility calculation, kinetic Monte-Carlo and others. NESS can also consider various sources of statistical variability in nanoscale devices and can perform simulations of large number of microscopically different devices created by the structure generator. I’ll summarize the workings of the different modules and demonstrate of the capabilities of NESS by presenting results obtained from the simulation of state-of-the-art and emerging devices.